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Est. 1988



cPCI2PMC - cPCI to PMC Adapter / Carrier


cPCI2PMC cPCI and PMC Compatible Adapter Carrier Front View 64 bit PCI bus version



The cPCI2PMC ( cPCI to PMC ) adapter / carrier converter card provides the ability to install a PMC card into a standard cPCI slot. The cPCI2PMC has a PMC card slot mounted to a universal 3U 4HP cPCI card. Suitable for 32/64 with 33/ 66 MHz bus operation. The PMC user IO connector Pn4 is optionally connected to J2 for rear panel IO. The PMC bezel connector is mounted though the cPCI mounting bracket. Optional Slot 0 operation with Bus Arbitration, Reset, clock distribution provided.

The cPCI bus is buffered with 10 ohm series resistors. The PCI clock is distributed with a zero delay buffer. The cPCI2PMC design is passive with no added delays to access the PMC hardware. The traces are carefully routed with proper attention paid to the impedance and reference planes to maximize compatibility with your cPCI system. The passive design of the cPCI2PMC reduces system latency.

The PCI bus is interconnected to the PMC via 64 bit 66 MHz capable layout. The slower and more narrow device will determine the interface characteristics. The M66EN jumper allows the user to specify the PCI speed capabilities. M66EN is interconnected between the cPCI bus, jumper, and PMC device.

The PCI VIO is interconnected to the PMC directly. The PCI backplane will determine the bus voltage reference. The voltage select pins are not installed on the cPCI2PMC and it is left to the user to properly select the PMC and cPCI motherboard for cPCI voltage level considerations. Many PMCs are "universal" and can work with 3.3 or 5V cPCI backplanes. If you need to use a 3.3V card on a 5V backplane or vice-versa please consider the cPCIBPMC3U64 design. The bridge implementation provides level shifting between the cPCI and PMC buses.

The cPCI2PMC follows the PMC specs for maximum power consumption and heat dissipation (7.5 watts). The power is routed from the cPCI to PMC connectors with mini-planes each of which is rated for more than the maximum PMC draw. 3.3, 5, VIO, +12, -12

The individual pins on the JN4 (PN4) connector are accessible when the IO option is specified. With cPCI J2 has two definitions - in a 64 bit PCI implementation J2 has the upper A/D and control signals and in a 32 bit PCI implemention J2 has the rear panel IO. With resistor jumpers the IO or the PCI signals can be connected to J2. Please be sure to specify -IO, -64, or blank [ neither].

If you have custom requirements please call or e-mail us with the details.


cPCI2PMC Features

  • Size
    		•  3U 4HP cPCI

  • PMC compatible slot
    		•  1 PMC Slot provided.

  • Clocks
    		•  cPCI bus can operate at 66 or 33 MHz. The PMC must be 66 MHz capable for 66 MHz operation to work properly. M66EN has a user shunt to allow or disable 66 MHz. operation.

  • Access Width
    		•  Standard cPCI byte lanes supported for byte, word and long access dependent on installed PMC. 64 or 32 bit operation supported.

  • Software Interface
    		•  PMC register definitions as defined by installed hardware. No software set-up required by cPCI2PMC.

  • Interrupts
    		•  INTA, B, C, D routed to cPCI connector from PMC.

  • Signal Conditioning
    		•  AD signals are series terminated with 10 ohm resistors. Zero delay buffer for PCI clock distribution.

  • Power
    		•  +5, +3.3, +12, -12V VIO supplied to PMC.

  • VIO
    		•  PCI IO Voltage is set by the PCI backplane. VIO is routed from the PCI connector to the PMC.

  • Thermal
    		•  The cPCI2PMC is a passive design with minimal heat dissipation for optimal PMC performance.

  • IO Interface
    		•  Front Bezel IO supported at cPCI bracket. Jn4 "user IO" supported with interconnection to J2 when -J2 option specified.

  • LEDs
    		•  +3V, +5V, +12V, -12V and Busmode 1.

  • JTAG
    		•  JTAG header connected to PMC supplied. JTAG pin definitions are in the silkscreen.




    cPCI2PMC Benefits

  • Speed
    		•  Now you have a choice between the cPCI2PMC and the cPCIBPMC. With the cPCI2PMC direct connect to the PCI bus the latency to the PMC is optimized. With the Bridged design of the cPCIBPMC the system speed is optimized. In some cases the possibility of doing 64 bit accesses to 32 bit PMC ports [memory] and 66 MHz primary PCI with a 33 MHz PMC secondary may be faster than the direct connect model. In either case your data will move quickly and reliably through the PCI bus to and from your hardware.

  • Price
    		•  The cPCI2PMC has the low price point. Make use of existing PMC designs in cPCI applications without paying for the expense of a new design and layout. Quantity discounts are available. Three basic versions are available. No J2, J2 IO and J2 cPCI extension.

  • Warranty
    		•  1 year warranty

  • Ease of Use
    		•  The cPCI2PMC is easy to use. A plug and play interface to the PMC site.

  • Availability
    		•  The cPCI2PMC is a popular board. We keep the cPCI2PMC in stock. Send in your order and in most cases have your hardware the next day - delivered to you via FedEx.

  • Size
    		•  The cPCI2PMC is a 3U 4HP cPCI board which conforms to the cPCI mechanical specifications. Eliminate mechanical interference issues. The cPCI2PMC can be used in all cPCI slots.

  • PMC Compatibility
    		•  The cPCI2PMC is PMC compliant per the IEEE 1386 specification. All Dynamic Engineering PMC Modules are compatible with the cPCI2PMC.

  • cPCI Compatibility
    		•  The cPCI2PMC is not cPCI compliant. The cPCI2PMC has trace lengths slightly in excess of the maximum specified by the PCI specification. The cPCI2PMC design includes several features to minimize the effects of the longer traces. The zero delay clock buffer keeps the PCI side of the clock length within specification, and the 10 ohm series resistors help to control the AD and control signals. All cPCI bus signals are properly referenced to planes.

    Single cPCI2PMC adapters can be expected to work in any PCI bus stub. If you need to operate multiple adapters per stub we recommend the cPCIBPMC which is completely cPCI specification compliant. The cPCI2PMC is based on the PCI2PMC which is in use in hundreds of chassis and tested in multiple backplanes. The cPCI2PMC is closer to specification than the PCI2PMC. Due to the mechanical configuration a passive design will not meet all of the length specifications.



    cPCI2PMC Standard Version with Bezel IO 32 bit PCI bus

    cPCI2PMC Ordering Options
    Using the drop down menus, select your board build options and Accessory options.

    Quantity
  • cPCI2PMC:Standard cPCI2PMC J2 not installed, IO through Bezel (front panel).

  • cPCI2PMC-IO: J2 installed and connected to Jn4 with standard rear panel IO definitions

  • cPCI2PMC-IOJn3: J2 installed and connected to Jn4 with standard rear panel IO definitions. Jn3 is also installed.

  • cPCI2PMC-64 option: J2 installed and connected to Jn3 for upper cPCI bus signals

  • cPCI2PMC-64Jn4 option: J2 installed and connected to Jn3 for upper cPCI bus signals. Jn4 also installed


  • cPCI2PMC-M option: Monarch capability with PMC receiving clock input from added oscillator. System clock driven by cPCI2PMC. 33mhz

  • cPCI2PMC-M-IO option: Monarch capability with PMC receiving clock input from added oscillator. System clock driven by cPCI2PMC. 33mhz. J2 installed and connected to Jn4 with standard rear panel IO definitions

  • cPCI2PMC-M-64 option: Monarch capability with PMC receiving clock input from added oscillator. System clock driven by cPCI2PMC. 33mhz. J2 installed and connected to Jn3 for upper cPCI bus signals

  • cPCI2PMC-M-66 option: Monarch capability with PMC receiving clock input from added oscillator. System clock driven by cPCI2PMC. 66mhz

  • cPCI2PMC-M-66-IO option: Monarch capability with PMC receiving clock input from added oscillator. System clock driven by cPCI2PMC. 66mhz. J2 installed and connected to Jn4 with standard rear panel IO definitions

  • cPCI2PMC-M-66-64 option: Monarch capability with PMC receiving clock input from added oscillator. System clock driven by cPCI2PMC. 66mhz. J2 installed and connected to Jn3 for upper cPCI bus signals

  • cPCI2PMC-M1 option: Monarch capability with PMC driving PCI clock. System clock driven by PMC installed onto cPCI2PMC.

  • cPCI2PMC-M1-IO option: Monarch capability with PMC driving PCI clock. System clock driven by PMC installed onto cPCI2PMC. 33mhz. J2 installed and connected to Jn4 with standard rear panel IO definitions

  • cPCI2PMC-M1-64 option: Monarch capability with PMC driving PCI clock. System clock driven by PMC installed onto cPCI2PMC. 33mhz. J2 installed and connected to Jn3 for upper cPCI bus signals

  • cPCI2PMC-M1-66 option: Monarch capability with PMC driving PCI clock. System clock driven by PMC installed onto cPCI2PMC. 66mhz

  • cPCI2PMC-M1-66-IO option: Monarch capability with PMC driving PCI clock. System clock driven by PMC installed onto cPCI2PMC.66mhz. J2 installed and connected to Jn4 with standard rear panel IO definitions

  • cPCI2PMC-M1-66-64 option: Monarch capability with PMC receiving clock input from added oscillator. System clock driven by cPCI2PMC. 66mhz. J2 installed and connected to Jn3 for upper cPCI bus signals.

  • cPCI2PMC-IO-SLT0: J2 installed and connected to Jn4 with standard rear panel IO definitions, plus slot 0 functions: bus arbitration, reset, clock distrbution

  • cPCI2PMC-64-SLT0: J2 installed and connected to Jn3 for upper cPCI bus signals plus slot 0 functions: bus arbitration, reset, clock distrbution


    cPCI2PMC Rear IO version

    The Monarch version of the cPCI2PMC has an oscillator installed to provide the PCI clock to the backplane and to the PMC installed. The Monarch pin [Pn2-64] is pulled down with a high value resistor. The M1 version allows the PMC to drive the PCI clock. The M and M1 options are designed for prPMC devices. This option is useful for simple systems not requiring the full slot zero capability.

    The System Slot version of the cPCI2PMC has the added capability to monitor the Bus Request signals, issue bus grants, create the system reset, and drive the clock signals to the approapriate J1, J2 pins per the cPCI slot 0 specification. The base design incorporates the features. The parts associated with the slot zero capability are not installed when this option is not requested. Please note that a PrPMC can be installed into the PMC slot. The PrPMC will need to take care of bus enumeration and other slot 0 functions associated with the system processor.



    cPCI2PMC rear view of -IO version

    You must have Adobe Acrobat 4.x to read our PDF files.

    Download the cPCI2PMC Manual 4/14/05 in PDF format.

    Related:
    cPCIBPMC3U64 cPCI 3U 4HP Bridged 64 bit PMC carrier with optional ethernet wiring to backplane
    cPCIBPMC3U64ET cPCI 3U 4HP PMC carrier with Extended Temperature
    cPCIBPMC6UET cPCI 6U 4HP dual PMC carrier with Extended Temperature

    Custom, IP, PMC, PC*MIP, PCI, VME Hardware, Software designed to your requirements



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