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Dynamic Engineering's Industrypack Compatible Designs

IP-OctalSerial



Highest density serial IP

Do you have density challenges? Need more channels and fewer slots? IP Octal Serial is an IndustryPack® design with enough IO, memory, and FPGA support to provide 8 channels of IO. There are 8 FIFO positions with a standard 32K x 16 FIFO installed, 24 differential transceivers, and a Spartan II FPGA. When combined with a PCI5IP 40 channels of IO can be installed in a single PCI slot or 32 in a single cPCI slot with the cPCI4IP.

The transceivers are rated at 40 MHz and the bus interface can run at 8 or 32 MHz. High speed serial IO can be implemented and sustained with the 32 MHz IP interface coupled with the large FIFO´s. With the Dynamic Engineering IP carrier "FAST" technology 32 bit PCI transfers can be used for read and write operations further enhancing the speed of operation.

The IP-OctalSerial is not for everyone. Many designs can be supported with the IP-Biserial with the equivalent of 2 channels. If you need more than 2, the IP-OctalSerial will be a cost effective and space saving solution for you.

The IP-OctalSerial design is readily available. The designs listed are available as "off-the-shelf" and custom versions can usually be accomplished with VHDL modifications. Many of the updates/custom versions you see on the various Dynamic Data Pages have been accomplished in 1-2 weeks. Contact us with your requirements for the IP-OctalSerial.





IP-OctalSerial Features

  • Size
    		•  single slot Type 2 IP Module [max height on rear = .055" / 1.4 mm].

  • IO
    		•  24 independent RS485/RS422 transceivers. 40 MHz max. Programmable termination. Unused bits can be used as a parallel port.

  • Speed
    		•  8 and 32 MHz IP bus operation. Up to 40 MHz on IO.

  • IP decoding
    		•  ID, IO, Mem and INT spaces supported

  • Memory
    		•  8 FIFOs are supplied - one per channel. The FIFOs are designed to support independent operation on each channel.

  • Clocks
    		•  Internally generated and externally supplied clocks are supported with source selection and programmable divider.

  • Access Width
    		•  all addresses are on 16 bit boundaries

  • ID PROM
    		•  Each version of the IP-OctalSerial has a unique ID PROM for identification.

  • Write cycle to TX FIFO
    		•  Write cycles to the FIFO are supported with a write through buffer. Also multiple FIFOs can be loaded with a single write operation when the same data set is to be sent from multiple ports.

  • Write cycle to RX FIFO
    		•  Write cycles to the RX FIFO are supported for loop-back testing.

  • Software Interface
    		•  All registers are read-write. All registers on word addresses. Each channel has the same relative bit definitions. Each channel as separate control registers.

  • Interrupts
    		•  Programmable interrupts for each channel are supported. Masked interrupts can be used in polled mode by reading the status register. Interrupts are mapped to INTR0n on IP bus.

  • Power Requirement
    		•  +5V

  • Oscillator
    		•  Provision for a local oscillator to generate custom frequencies.

  • MTBF
    		•  1.49 million hours Bellcore SR332 MTBF


    IP-OctalSerial Benefits

  • Speed
    		•  The transmit memory can be loaded quickly. 32 bit accesses are supported by loading from the memory space. Multiple FIFOs can be loaded in parallel. Data write through is supported. Reading from the RX FIFO has also been optimised to support high speed operation. 32 and 8 MHz IP clock rates are supported. The Xilinx can handle high speed serial or parallel protocols. The IO are rated at 40 Mhz.

  • Price
    		•  The IP-OctalSerial has the low price point. Up to 8 channels in one slot means fewer slots used. Fewer slots and higher performance are a winning combination.

  • Ease of Use
    		•  The OCTALSERIAL is easy to use. Please download the manual and see for yourself. The engineering kit provides a good starting point for a new user. The reference software does a loop-back test and set-ups the different modes of operation.

  • Availability
    		•  The IP-OctalSerial is a popular board. We keep the IP-OctalSerial in stock. Send in your order and in most cases have your hardware the next day - delivered to you via FedEx.

  • Size
    		•  The IP-OctalSerial in standard configuration is a Type 2 size IP module which conforms to the IndustryPack mechanical and electrical specifications. Only .055" on the rear means no mechanical interference issues. The IP-OctalSerial can be used in all IP slots.

  • IP Compatibility
    		•  The IP-OctalSerial is IP compliant per the VITA 4 - 1995 specification. All Dynamic Engineering IP Modules are compatible with the PCI3IP and PCI5IP. The IP-OctalSerial will operate with any IP specification compliant carrier board.


    Ordering Information
    IP-OctalSerial
    IP-OctalSerial has 8 FIFO supported differential IO channels and a large programmable Xilinx FPGA to support custom state-machine implementations.

    Quantity


    Engineering Kit

    IP-OctalSerial-ENG..........Engineering Kit for IP-OctalSerial includes:
    Board level Schematics [PDF], Reference Software [IP-OctalSerial C test code ZIP file], IP-Debug-Bus, IP-Debug-IO. Software environment is Windows NT with WinRT and MS Visual C. WinRT and MS Visual C sold separately


    Manuals
    Download the     IP-OctalSerial Manual version FCS 03/18/08 in PDF format.


    Related Products

    IP-DEBUG-IO, HDRterm50, IP-DEBUG-BUS , IP-MTG-KIT (Mounting Hardware)


    Custom, IP, PMC, cPCI, PCI, PC*MIP, VME Hardware, Software designed to your requirements

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