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Dynamic Engineering's Industrypack Compatible Designs

IP-QuadUART-485



The IndustryPack compatible IP-QuadUART-485 design integrates a quad UART onto an IndustryPack module. The UART (16C854) features 128 byte FIFOs for RX and TX ports on each channel. The UART is supported by an advanced IP module interface implemented within a Xilinx FPGA.

The UART is a character based interface [8 bits]. The IndustryPack interface has several features which optimize performance. Words can be written to the IP-QuadUART-485 and the data will be coverted to bytes before being sent to the UART. The IP interface will latch the data allowing the host computer to be released while the data is being moved to the UART. The early release allows pipelined operation and increased performance. When the IP-QuadUART-485 is mounted to a carrier which supports 32 bit operations the effect can be enhanced. The PCI3IP, PCI5IP , and cPCI2IP and other Dynamic Engineering carriers support 32 bit access to IndustryPacks.

When reading data, the IP-QuadUART-485 supports 8, 16, and 32 bit accesses by assembling the bytes read from the UART into a register within the Xilinx. With 32 bit reads 1/4 of the data transfer cycles are needed. In the standard mode the data is read when the host performs the transfer cycle. An optional higher performance mode of operation is the pre-read mode. In pre-read the UART is read and the data stored within the Xilinx. With the data stored internal to the Xilinx the data can be accessed without waiting for the UART.

The IP-QuadUART-485 is compatible with 8 and 32 MHz IP bus interfaces. A speed select control bit optimizes the state machine for either frequency.

The IP-QuadUART-485 is compatible with RS-485 and RS-422 requirements. Software can select full and half duplex operation on each channel independently. The signals supported are RX, TX, CTS, RTS, DTR, DSR . Software has control over the "direction" of the TX and by placing in receive mode can configure for use in multi-drop or half-duplex systems. The RX signal is always an input. A mux is provided within the FPGA to select the RX or the TX input to allow for half-duplex. The direction control on the TX transceiver is used for multi-drop and half-duplex control. The RTS and DTR signals are always driven.

The UART IO is available at the IO connector. Most IP carriers route the IP module IO connectors to 50 pin headers to support ribbon cable. The HDRterm50 can be used to create a terminal block interface. In the future a transition module will be available with ribbon to 4 - D connectors, and DIN compatible.

Two local oscillators are provided to allow the full range of the UART to be utilized. 24 MHz and 18.432 Mhz oscillators provide 1.5 M max rate with RS-422 and all of the standard baud rates.



IP-QuadUART-485 Features

  • Size
    		•  single slot IP Module

  • UART Channels
    		•  4 full UART channels are provided

  • Interface
    		•  Each of the 4 UART ports can be selected to be half or full duplex compatible with software. Any combination of channels is valid.

  • Speed
    		•  Each channel can operate up to 1.5M.

  • Enables
    		•  TX drivers can be enabled or disabled. Disable for internal loop-back test without broadcasting and for multi-drop [RS-485] operation.

  • Termination
    		•  Each of the channels have a termination on the RX, CTS, and DSR. TX is not terminated on the card. In multi-drop mode the terminations should be supplied in the cable.

  • Clocks
    		•  8 and 32 MHz operation IP Module bus operation.

  • Access Width
    		•  ID PROM is byte wide, internal control register is word wide, UART is byte wide.

  • ID PROM
    		•  The IDPROM is build into the Xilinx. The "PROM" contents are available to determine the current revision of the IP-QuadUART and to determine the slot location. The user manual has the expected data content definition.

  • Write cycle
    		•  The write cycle to the QuadUART is pipelined with an early termination to the IP host. The pipelining reduces the access time in writing to the UART FIFO memory. Byte expansion from words is supported.

  • Read cycle
    		•  Read cycles wait for data to be available from the UART or can be selected to pre-read the data to support higher performance operation. Byte packing into words is supported.

  • Software Interface
    		•  Control registers are read-writeable
    IO, ID, INT spaces supported.

  • Interrupts
    		•  Interrupt level 0 is used to route the QuadUART interrupt to the host computer. The interrupt is maskable and pollable.

  • Power Requirement
    		•  +5V

  • Oscillator
    		•  Two oscillators are provided to cover the full frequency range of UART and extended operations. The oscillator frequencies [24 and 18.432] can be changed upon request. Custom versions with special frequency requirements can be supported.



    IP-QuadUART-485 Benefits

  • Speed
    		•  The IP-QuadUART-485 is compatible with 8 and 32 MHz IP reference rates with write through to UART capability. The UARTs have deep FIFOs to support the higher bandwidth. Use with the PCI3IP, PCI5IP , or cPCI2IP for maximum throughput. High baud rates are supported in half and full duplex modes of operation. Why wait for the competition when you can be done with Dynamic Engineering.

  • Price
    		•  The IP-QuadUART-485 has the low price point. Add 4 high speed UARTs with memory and a flexible electrical interface in one slot where other solutions take several. Fewer slots and fewer dollars are a winning combination.

  • Ease of Use
    		•  The QuadUART-485 is easy to use. A point and shoot user interface to the UART. Please download the manual and see for yourself. The engineering kit provides a good starting point for a new user. The reference software does a loop-back test and set-ups the different modes of operation.

  • Availability
    		•  The IP-QuadUART-485 is a popular board. We keep the IP-QuadUART-485 in stock. Send in your order and in most cases have your hardware the next day - delivered to you via FedEx.

  • Size
    		•  The IP-QuadUART in is single slot IP module which conforms to the IndustryPack mechanical and electrical specifications. The IP-QuadUART-485 can be used in all IP slots.

  • IP Compatibility
    		•  The IP-QuadUART-485 is IP compliant per the VITA 4 - 1995 specification. All Dynamic Engineering IP Modules are compatible with the PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP and the rest of the Dynamic Engineering carriers. The IP-QuadUART-485 will operate with any IP specification compliant carrier board.


    Ordering Information

    Engineering Kit

    Quantity


    IP-QuadUART-485-ENG..........Engineering Kit for IP-QuadUART-485 includes:
    Board level Schematics [PDF], Reference Software [IP-QuadUART C test code ZIP file], IP-Debug-Bus, IP-Debug-IO. Software environment is Windows NT with WinRT and MS Visual C. WinRT and MS Visual C sold separately


    Download the IP-QuadUART-485 Manual 12/23/02 in PDF format.


    Custom Versions of the IP-QuadUART-485

    The IP-QuadUART-485 has a Xilinx Spartan II, QuadUART device plus RS-485 IO. The UART can be removed and the IO connected directly to the Xilinx to allow alternate designs to be implemented. The UART footprint has jumper locations designed in to allow resistor jumpers to be used instead of rework wire in many cases. The Xilinx has room for state-machines, FIFOs etc.

    IP-QuadUART-485-BA7
    Customer - Boeing

    The IP-QuadUART-485-BA7 is part of the IP Module family of modular I/O components. It is based on the IP-QuadUART-485 with the UART and all of the IO removed, except for eight RS-485 transceivers. Also the Xilinx FPGA has been upgraded to an XC2S100.

    The module consists of four independent channels that receive Manchester encoded data consisting of 16-bit words plus one parity bit using RS-485 transceivers. Each channel also contains a transmitter to send test data with the same format. The data is sent msb first at a 1 Mbit rate with a preceding 3-bit start/sync pattern. The marking state of the link is low and the start pattern consists of a 1 bit high level followed by a 1 bit low level. Odd parity is used

    Each channels data is stored in a 16-bit by 512 word FIFO as it is received. The transmit data is stored in a read/write register and sent by a self-clearing bit in the channel control register. There is also a control bit to enable sending the data twice in succession with a 12 microsecond delay between words. This tests the ability of the receiver to detect closely spaced data transmissions.

    The IP-QuadUART-485-BA7 is supported with the carrier driver and IP driver for windows®.
    Download the IP-QuadUART-485-BA7 Manual 8/30/05 in PDF format.
    Download the IP-QuadUART-485-BA7 Windows® Driver Manual 8/30/05 in PDF format.

    IP-QuadUART-485-PA2
    Customer - Phillips Aerospace

    The IP-QuadUART-485-PA2 is part of the IP Module family of modular I/O components. It is based on the IP-QuadUART-485 with the UART and all of the IO removed except for two RS-485 transceivers. Also the Xilinx FPGA has been enhanced to an XC2S100 in order to have enough internal block-RAM to accommodate the design.

    The module consists of two independent interfaces that send and receive 16-bit words using RS-485 transceivers. The data is sent msb first at a 4 Mbit rate with one preceding start bit. The marking state of the link is low and the start bit is high.

    The target interface is the focus of the module, but a master interface is also implemented to allow for standalone testing of the module.

    All transactions are instigated by the master interface and consist of either a read or a write command and a 16-bit data word to be written to a write register, or that was read from a read register. The module has 64 read registers at offset 0 - 0x7E in the IP MEM space, and 64 write registers at offset 0x80 - 0xFE. These registers can be both written and read from the IP bus, but can only be read or written over the RS-485 bus.

    The IP-QuadUART-485-PA2 is supported with the carrier driver with the generic IP driver for windows®.
    Download the IP-QuadUART-485-PA2 Manual 10/13/04 in PDF format.


    IP-QuadUART-485-DSP1
    Customer - DSP
    The module consists of two independent channels that receive Manchester encoded data consisting of 32-bit words plus one parity bit using RS-485 transceivers. Each channel also contains a transmitter to send test data with the same format. The data is sent lsb first at a 1, 2, 3, or 4 Mbit/sec rate with a preceding 3-bit start/sync pattern and a following parity bit. The default clock rate is 2 Mbit/sec and the parity can be either even or odd controlled by a bit in the channel control register. The first word of a message has a transition from high to low in the center of the 3-bit sync pattern, bits 8 to 0 are the message ID field, and bits 17 to 9 are the number of words in the message. This number includes the start of message word but not the final word of the message which is the CRC of the message. Therefore the number of words field will be one less than the total number of words in the message. All the words in the message besides the first have a transition from low to high in the center of the 3-bit sync pattern.

    Each channelšs data is stored in a 1K by 16-bit FIFO as it is received. The transmit data is stored in a 256 by 16-bit FIFO and sent by a self-clearing bit in the channel control register. It is assumed that the transmit FIFO contains a single complete message, so the first word sent is treated as the first word of a message and the FIFO data is sent continuously until the FIFO is empty.

    A 32-bit counter running at 2 MHz is available to assign time-stamps to received messages. The counter is enabled and cleared by control bits in the base control register. The count can be read at any time from two status ports that each return 16-bits of the count. A control bit in the channel control registers enables saving the time-stamp count for each message to the receive FIFO following the message data. The count is latched as soon as the start-of-message sync is detected and that value is written to the receive FIFO after the end of the message with two successive 16-bit writes. The least significant 16 bits is written first followed by the most significant 16 bits.

    Download the IP-QuadUART-485-DSP1 HW Manual in PDF format.
    Download the IP-QuadUART-485-DSP1 Driver Manual in PDF format.

    IP-QuadUART-485-PLR
    Party Line Interface The PLR interface provides communication with a DRC11-C interface that resides in a PDP-11 computer. The IP-QuadUART-485-PLR can be integrated into a PC, using a PCI IP carrier such as the PCI3IP. The IP-QuadUART-485-PLR generates a 24-bit serial word out, and receives a 16 bit data word from a variety of custom units. The 8 TTL bidirectional signals are user programmable with COS capability. Interrupt generation capability. The clock and data lines are 485 I/O signals. Monitor and strobe signals are generated under user control, and are single ended TTL signals.

    The PLR can function as a master or target or both. As a master, there are three modes of operation. The strobe and monitor signals can be programmed to be active or suppressed to provide transmit/receiver (both active), transmit only(monitor not active), or receive only(strobe not active). The PLR design also implements a target to facilitate loop back testing. The target will capture transmitted data at 2Mhz and 8Mhz and provide data when monitor is active.
    Download the IP-QuadUART-485-PLR HW Manual in PDF format.
    Download the IP-QuadUART-485-PLR Driver Manual in PDF format.



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