IP-OptoISO-16

IndustryPack® Modules are an important part of solutions for Embedded situations. Rugged, small, light, just right for many applications. IP-OptoISO-16 is an IndustryPack Module with 16 optically controlled FET´s [switch]. Each FET acts as a single pole normally open photovoltaic relay. The solid state approach has several advantages including bounce free operation, low on resistance, long life, fast switching, and higher reliability when compared to relays. The design utilizes a Xilinx FPGA to provide the IP interface - IDPROM, Bus interface, registers, and control for the FETs. Each optical switch has a separate bit in the control register to allow for independent operation.

The FET´s switch the Drain and Source. The Drain or Source for each switch is tied to a reference voltage. When the switches are closed the S is connected to D. The voltage range is 0-60 VDC. Each switch can handle 1.5A. The traces on the IP are rated for 1.5A. Please check with your IP carrier for maximum current capabilities. Please contact Dynamic Engineering if you need a carrier with power traces.




The Source is DIODE coupled to the Drain within the optoisolator device and DIODE coupled [100V,30A] to system ground. The DIODE´s provide protection when controlling inductive loads. Once side affect is that the Drain voltage should be the same as or higher than the Source voltage. For a high side switch the Drain side should be referenced to the system voltage and the source tied to the switched input. For a low side switch the Source should be tied to the lower voltage [usually ground] and the Drain side tied to the switch input. An external pull-up or pull-down can be used to control the level when the switch is in the off state.

IP-OptoISO-16 has a separate FET used to enable the optical side of the switch. The FET is controlled by the Xilinx and is designed to reset to the off condition to prevent potential output glitches during initialization. The enable can also be used as a master on-off mechanism by the software.

The software interface is very simple. One control bit for the Optical power enable and 16 bits to control the outputs. In addition to the output control are the timer controls. The count reference registers can be set to control the counter/timer operation.

IP-OptoISO-16 design supports an enhanced MC68230 capability with two - 32 bit counter - timers. The counter-timers are easy to use with a minimum of registers to access and complete independence. The IP clock is used as a reference; both 8 and 32 MHz can be used.

Counter/Timer A features a 32 bit down-counter with a pre-load register. The counter output is tested against a "zero" value. When zero the counter is re-loaded with the pre-load value to create a cycle. At each zero detection an interrupt can be generated. At each zero detection a waveform can be transitioned. The waveform can be enabled onto any of the outputs.


IP-OptoISO-16 Counter - Timer A Block Diagram


Counter / Timer B has a 32 bit up counter which can be cleared by the software. The counter output is masked with a user programmable value to select a particular counter bit or bits to use for interrupt creation. The counter output is also available to read via software and can serve as a real-time clock.


IP-OptoISO-16 Counter - Timer B Block Diagram

There is ample room within the FPGA to add custom state-machines etc. as your needs require.
Please contact Dynamic Engineering with any special requirements.

The IP Module driver can be instantiated multiple times to control multiple cards by the same CPU. IP-OptoISO-16 when coupled with the Dynamic Driver "knows" what slot it is in and which carrier it is installed into. The slot and carrier information is required when using multiple cards in a PCI/PCIe system with dynamic address assignment. A known system configuration can be combined with the slot and carrier information to deterministically access the right card

PCI implementations can be done with PCI3IP and PCI5IP. Applications from 1 to 80 Opto IO per PCI slot.
PCIe is supported with the PCIe3IP and PCIe5IP. Applications from 1 to 80 Opto IO per PCIe slot.
cPCI 3U is supported with cPCI2IP. Applications with 1 to 32 Opto IO per 3U cPCI slot.
cPCI 6U is supported with cPCI4IP. Applications from 1 to 64 Opto IO per 6U cPCI slot.
PC104p is supported with PC104pIP. Applications with 1 Opto IO per PC104 stack position.
PC104p situations with a custom mechanical can be done with the PC104p4IP.
Applications from 1 to 64 Opto IO per PC104 stack position.
3U VPX is supported with VPX2IP. Applications with 1 to 32 Opto IO per 3U VPX slot.
6U VPX is supported with VPX4IP. Applications from 1 to 64 Opto IO per 6U VPX slot.