150 Dubois St. Suite #3
Santa Cruz, Calif. 95060 (831) 457 8891 (831) 457 4793 Fax
Est. 1988
Dynamic Engineering's IP Compatible Designs IP-Parallel-BA1 "IP-Tape"
IP-Parallel-BA1 "IP-Tape" Block Diagram
The IndustryPack compatible IP-Tape design adds 48 digital parallel IO lines to one slot of your carrier board. The IO is dedicated to a DTC interface. Other interfaces can be implemented. The DTC interface has 22 Address, 16 Data plus Parity, 4 control and 5 status lines. Parity is automatically generated in write mode and checked in read mode. Parity is programmable to be old or even. Outputs in "tape" mode are driven with 64 mA open-drain devices. A 470 ohm pull-up resistor is provided on board. The registers are mapped as 16 bit words and are read-writeable.
The registers are mapped as 16 bit words. All registers are read-writeable.
IP-Tape IO Filter and Interrupt Control Block Diagram
All 48 IO channels can be used as interrupt generators. Interrupts are programmable to be enabled, active high or low, and edge or level triggered.
IP-Tape DTC Read Timing
The Timing can be altered with a change to the state-machine for other implementations. The state machine has counters to create the delays for each state. In this design, the counters are set to wait 4.5 uS after address is asserted to assert Address Enable [ENABLEn], then 1.5 uS before asserting Data Enable [DTC_ENA]. RW is asserted with ENABLEn. RW is high as a default and for read accesses. RW is asserted low for a write cycle. The Global enable [DTC_DECn] is asserted at the start of the cycle.
IP-Tape DTC Write Timing
Ordering Information
IP-Parallel-tape
Engineering Kits
Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. We recognize that different customers have different needs. The Engineering Kits are standardized in description to help with selection. The kits are segmented to allow for customers who only need hardware support, software support or a mixture. The Engineering Kit is highly recommended for first time buyers. The kit pricing is discounted to encourage their use.
IP-Tape-Eng-2 .......... Hardware Support plus Driver Engineering Kit includes:
Board level Schematics [PDF], Software[IP Driver and sample application zip file ], IP-Debug-Bus, IP-Debug-IO.
IP-Tape-Eng-3 .......... Hardware Support plus Driver and Carrier Engineering Kit includes:
Board level Schematics [PDF], Software [IP Driver and sample application zip file ], PCI3IP carrier card, PCI3IP Driver, IP-DEBUG-BUS, IP-DEBUG-IO.
IP-Tape-Eng-4 .......... Driver and Carrier Engineering Kit includes:
Software[IP Driver and sample application zip file ], PCI3IP carrier card, PCI3IP Driver
IP-Tape Drivers .......... Software Support Only Windows®XP and 2000 compliant drivers for the IP-Tape:
Driver and user application. Requires Carrier driver - sold separately. Download the IP-Tape/Crypto Window® Driver Manual updated 10/29/04
Related Products
Cable_Assem_Crypto/Tape PCI Bezel Connector for IP-Crypto and IP-Tape. IP-Debug-IO IP IO connector T&I tool, IP-Debug-Bus IP Extender card with test points, hot swap capability, power monitoring, HDRterm50 50 pin ribbon cable to terminal strip converter DIN rail mounting, HDRribn50 50 pin ribbon cable, PCI3IP 3 IP Module Carrier in 1/2 width PCI card, PCI5IP 5 IP Module Carrier in full width PCI card, cPCI2IP 2 IP Module Carrier in 3U cPCI card, PC/104pIP 1 IP Module Carrier in PC/104p card, IP-MTG-KIT stainless steel screws and standoffs to mount an IP to a carrier
