150 Dubois St. Suite #3
Santa Cruz, Calif. 95060
(831) 457 8891 (831) 457 4793 Fax
Est. 1988
Dynamic Engineering's IP Compatible Designs
IP-Parallel-HV
IP-Parallel-HV
| Single wide IP |
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| 24 open collector outputs. 40 mA sink., 6.5V reference STD |
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| Internal reference voltage up to 12 volts can be programmed. External references up to 30V. Diode protected for external source. 24 inputs. Resistor divider provided for 6.5V reference std. Other combinations are available. Series-parallel termination provided for maximum range adjustability |
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| 470 ohm on upper 8 bits, 1K ohm on lower 16 bits is standard |
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| 16 bit registers mapped to the IO channels. Word writeable. Read-back of channel control registers and input registers. Read-write of control register for card configuration. |
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| All input channels can be programmed to cause interrupts. Each channel is programmable to be masked, active hi, active low, edge or level sensitive. Interrupts are mapped to INTR0n on IP bus |
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| +12, +5 |
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| All IO Channels are protected with current limiting resistors. |
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| There is room in the FPGA for custom applications that need IO. Send in your specifications and we can quote a custom version for you |
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| Belcore 25c GB 1.855 Million Hours |
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