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150 Dubois St. Suite C
Santa Cruz, Calif. 95060
(831) 457 8891 (831) 457 4793 Fax
Est. 1988


Dynamic Engineering's IP Compatible Designs
PCI-Parallel cPCI-Parallel PC104p-Parallel VME-Parallel based on IP-Pulse

IP-Parallel-IO




IP-Parallel-IO Block Diagram


The IndustryPack compatible IP-Parallel-IO with counter and timer design provides 48 digital parallel IO lines in one IP module slot of your carrier board. These IO´s can be configured to be TTL or RS485 compatible in several combinations. A real space saver for systems with both types of IO. Perfect for your embedded control applications. Please download the manual [see bottom of page] for more information. IP-Parallel is available as an add-on IndustryPack Module for use with carriers on all of the common buses: VME, cPCI, PCI, and PC104p. IP-Parallel is supported for both Windows® and Linux.

PCI implementations can be done with the PCI3IP and PCI5IP.
Applications from 1 to 240 TTL lines and/or 1 - 120 Differential pairs per PCI slot.
cPCI 3U is supported with the cPCI2IP. Applications from 1 to 96 TTL lines and/or 1 - 48 Differential pairs per 3U cPCI slot.
cPCI 6U is supported with the cPCI4IP. Applications from 1 to 192 TTL lines and/or 1 - 96 Differential pairs per 6U cPCI slot.
PC104p is supported with the PC104pIP. Applications from 1 to 48 TTL lines and/or 1 - 24 Differential pairs per PC104 stack position.
PC104p situations with a custom mechanical can be done with the PC104p4IP.
Channel counts from 1 to 192 TTL lines and/or 1 - 96 Differential pairs per PC104 stack position.
3U VME is supported with the VME2IP. Applications from 1 to 96 TTL lines and/or 1 - 48 Differential pairs per 3U VME slot.
6U VME is supported with the VME4IP. Applications from 1 to 192 TTL lines and/or 1 - 96 Differential pairs per 6U VME slot.


IP-Parallel-485 Block Diagram


Each channel is programmable to be an input, or an output on a channel-by-channel basis via software. All DIO channels can be used as interrupt generators. Interrupts are programmable to be enabled, active high or low, and edge or level triggered. The registers are mapped as 16 bit words. All control registers are read-writeable.

Outputs in TTL mode are driven with 64 mA open-drain devices to allow multi-drop applications. 470 ohm pull-up resistors are provided. In 485 mode individual transceivers provide direction control and RS485 compatibility.

An external oscillator position is provided for custom applications.


IP-Parallel-IO IO Filter and Interrupt Control Block Diagram

Frequently it is necessary to correlate the time and the event. The IP-Parallel design supports an enhanced MC68230 capability with two - 32 bit counter - timers. The counter-timers are easy to use with a minimum of registers to access and complete independence. The IP clock is used as a reference; both 8 and 32 MHz can be used.

Counter/Timer A features a 32 bit down-counter with a pre-load register. The counter output is tested against a zero value. When zero the counter is re-loaded with the pre-load value to create a cycle. At each zero detection an interrupt can be generated. At each zero detection a waveform can be transitioned. The waveform can be enabled onto the upper data bit.


IP-Parallel-IO Counter - Timer A Block Diagram


Counter / Timer B has a 32 bit up counter which can be cleared by the software. The counter output is masked with a user programmable value to select a particular counter bit or bits to use for interrupt creation. The counter output is also available to read via software and can serve as a real-time clock.


IP-Parallel-IO Counter - Timer B Block Diagram



IP Parallel IO Features


  • Size
    		•  Single wide IP.

  • Parallel Interface
    		•  Up to 48 independent TTL and up to 24 Differential channels per module. Carrier determines number of modules that can be installed. Each channel can be an input or an output. Read-back filtered or direct.

  • IO Configuration
    		•  IO can be configured as single ended with open drain 64mA drivers and 470 ohm pull-ups or dfferential pairs.

  • Interface
    		•  BCT open drain drivers with 64mA current sink or 485 transceivers

  • Synchronization
    		•  Outputs can be synchronized to change together [across register boundaries]. Synchronization can be disabled.

  • Pull-up Resistor
    		•  470 standard, 1K, 4.7K available on TTL lines.

  • Counter / Timer
    		•  Two independent Counter / Timer functions are provided.
    CTA: 32 bit down-counter with registered initial value and auto-preload. Waveform generator. Interrupt generator based on zero detection. CTB: 32 bit up-counter with clear and read-back. Bitwise selectable interrupt generator.

  • Cable interface
    		•  IndustryPack standard IO

  • Software Interface
    		•  16 bit registers mapped to the 48 IO channels. Word writeable. Read-back of channel control registers and input registers. Read-write of control registers for card configuration.

  • Interrupts
    		•  All IO Channels can be programmed to cause interrupts. Each channel is programmable to be masked, active hi, active low, edge or level sensitive. Master enable for data channels. Separate enable for each data channel, CTA, and CTB. Status register with current interrupt request status. Interrupts are mapped to INTR0n on IP bus. Master enable can be disabled to allow polled operation.

  • Power Requirement
    		•  +5V. Approximately 52 mA typical unloaded.

  • Protection
    		•  All IO Channels are protected with current limiting resistors.

  • Custom
    		•  There is room in the FPGA for custom applications that need IO. Send in your specifications and we can quote a custom version for you



  • MTBF
    		•  1.496 million hours GB 25C Bellcore MTBF



    Order Information
    -TTL 48 TTL IO
    -1 40 TTL IO and 4 differential pairs
    -2 32 TTL IO and 8 differential pairs
    -3 24 TTL IO and 12 differential pairs
    -4 16 TTL IO and 16 differential pairs
    -5 8 TTL IO and 20 differential pairs
    -485 24 differential pairs
    -CDU CDU looping


    Please select card version & Eng. kit choices below:

    Quantity



    IP Parallel IO Benefits

  • Speed
    		•  Direct mapped IO, efficient IP interface, and dual IP bus speed compatibility provide an optimised interface.

  • Price
    		•  The IP-Parallel-IO is inexpensive and can save money in other ways too. The IP Parallel IO can take the place of three other IPs with its combination of TTL, 485, and counter timer functions; save slots and cash.

  • Ease of Use
    		•  The IP-Parallel-IO is easy to use. A point and shoot user interface. Please download the manual and see for yourself. The engineering kit provides a good starting point for a new user.

  • Availability
    		•  The IP-Parallel-IO is a popular design. We keep the IP-Parallel-IO and the -number versions in stock. Send in your order and in most cases have your hardware the next day - delivered to you via FedEx.

  • Size
    		•  The IP-Parallel is a standard size IP module. Combining three functions in one can make it the equivalent of 3 IP cards in one slot. A customized version could do even more to reduce your system size.

  • IP Compatibility
    		•  The IP-Parallel-IO is IP compliant per the VITA 4 - 1995 specification. All Dynamic Engineering IP Modules are compatible with the PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, etc. The IP-Parallel-IO will also be compatible with other carriers which are compliant with the VITA specification.


    Engineering Kits


    Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. We recognize that different customers have different needs. The Engineering Kits are standardized in description to help with selection. The kits are segmented to allow for customers who only need hardware support, software support or a mixture. The Engineering Kit is highly recommended for first time buyers. The kit pricing is discounted to encourage their use.

    IP-Parallel-Eng-1 .......... Hardware Support Engineering Kit includes:
    Board level Schematics [PDF], IP-Debug-Bus, IP-Debug-IO.

    IP-Parallel-Eng-2 .......... Hardware Support plus Driver Engineering Kit includes: Board level Schematics [PDF], Software[IP-Parallel Driver and sample application zip file ], IP-Debug-Bus, IP-Debug-IO.

    IP-Parallel Driver.......... Software Support Only Windows®XP and 2000 compliant drivers for the IP-Parallel: The driver is designed to work with a carrier driver - PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC/104p4IP etc. Requires Carrier driver - sold separately. Linux supported with carrier driver and generic mode module.

    Save money and buy the carrier with the IP. Free carrier driver included when [Dynamic Engineering] carrier is purchased with the IP Module. Pick Windows® or Linux support.


    Related Products
    IP-Debug-IO IP IO connector T&I tool,
    IP-Debug-Bus IP Extender card with test points, hot swap capability, power monitoring,
    HDRterm50 50 pin ribbon cable to terminal strip converter DIN rail mounting,
    HDRribn50 50 pin ribbon cable,
    IP-MTG-KIT stainless steel screws and standoffs to mount an IP to a carrier

    Quantity discounts available

    Custom Requirements Custom, IP, PMC, PC*MIP, PCI, VME Hardware, Software designed to your requirements

    Try before you buy program



    You must have Adobe Acrobat to read our PDF files.
    Download the IP-Parallel-IO Manual Standard Product Manual
    Download the IP-Parallel-IO Driver Manual for Windows

    Customer Special Versions
    You can order these too or request that we design one for you

    IP Parallel IO version BA1 "Tape"
    Customer: Boeing
    Interface with a cartridge tape device. Memory access to IP triggers data transfer with cartridge. 22 Address, 16 Data, 1 Parity, 4 control bits, 5 Status read and write cycles supported.

    Download the IP-Parallel-BA1 "Tape" Manual in PDF format

    Download the IP Tape XP/2000 Driver Manual in PDF format.


    Customer: Lockheed Martin
    IndustryPack® based interface to LARS CDU [Lightweight Airborne Recovery System Control Display Unit]

    When the IP-Parallel-CDU is powered-on it defaults to a dedicated serial interface that uses four IO lines to implement a full-duplex NRZ serial clock and data protocol. The transmit interface defaults to 32-bit LSB first at 500 kHz bit rate. Both the clock rate and the number of bits are programmable. The receive interface uses an external clock at a nominal rate of 614 kHz, and will function over a wide range of frequencies. The receive words default to 32-bits LSB first. The word size is programmable.

    Download the IP-Parallel-CDU Manual


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