IP-Parallel-IO
IP-Parallel-IO Block Diagram
knowswhat slot it is in and which carrier it is installed into. The slot and carrier information is required when using multiple cards in a PCI system with dynamic address assignment. A known system configuration can be combined with the slot and carrier information to deterministically access the right card.
zerovalue. When zero the counter is re-loaded with the pre-load value to create a cycle. At each zero detection an interrupt can be generated. At each zero detection a waveform can be transitioned. The waveform can be enabled onto the upper data bit.
| Single wide IP. |
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| Up to 48 independent TTL and up to 24 Differential channels per module. Carrier determines number of modules that can be installed. Each channel can be an input or an output. Read-back filtered or direct. |
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| IO can be configured as single ended with open drain 64mA drivers and 470 ohm pull-ups or dfferential pairs. |
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| BCT open drain drivers with 64mA current sink or 485 transceivers |
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| Outputs can be synchronized to change together [across register boundaries]. Synchronization can be disabled. |
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| 470 standard, 1K, 4.7K available on TTL lines. |
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| Two independent Counter / Timer functions are provided. CTA: 32 bit down-counter with registered initial value and auto-preload. Waveform generator. Interrupt generator based on zero detection. CTB: 32 bit up-counter with clear and read-back. Bitwise selectable interrupt generator. |
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| IndustryPack standard IO |
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| 16 bit registers mapped to the 48 IO channels. Word writeable. Read-back of channel control registers and input registers. Read-write of control registers for card configuration. |
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| All IO Channels can be programmed to cause interrupts. Each channel is programmable to be masked, active hi, active low, edge or level sensitive. Master enable for data channels. Separate enable for each data channel, CTA, and CTB. Status register with current interrupt request status. Interrupts are mapped to INTR0n on IP bus. Master enable can be disabled to allow polled operation. |
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| +5V. Approximately 52 mA typical unloaded. |
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| All IO Channels are protected with current limiting resistors. |
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| There is room in the FPGA for custom applications that need IO. Send in your specifications and we can quote a custom version for you |
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| 1.496 million hours GB 25C Bellcore MTBF | |
| Direct mapped IO, efficient IP interface, and dual IP bus speed compatibility provide an optimised interface. |
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| The IP-Parallel-IO is inexpensive and can save money in other ways too. The IP Parallel IO can take the place of three other IPs with its combination of TTL, 485, and counter timer functions; save slots and cash. |
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| The IP-Parallel-IO is easy to use. A point and shoot user interface. Please download the manual and see for yourself. The engineering kit provides a good starting point for a new user. |
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| The IP-Parallel-IO is a popular design. We keep the IP-Parallel-IO and the -number versions in stock. Send in your order and in most cases have your hardware the next day - delivered to you via FedEx. |
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| The IP-Parallel is a standard size IP module. Combining three functions in one can make it the equivalent of 3 IP cards in one slot. A customized version could do even more to reduce your system size. |
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| The IP-Parallel-IO is IP compliant per the VITA 4 - 1995 specification. All Dynamic Engineering IP Modules are compatible with the PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, etc. The IP-Parallel-IO will also be compatible with other carriers which are compliant with the VITA specification. |
