. The voltage range is 0-60 VDC. Each switch can handle 1.5A. The traces on the IP are rated for 1.5A. Please check with your IP carrier for maximum current capabilities. Please contact Dynamic Engineering if you need a carrier with power traces.
8/2005 New Product Announcement: PMC-BiSerial-III
The PMC BiSerial family has been updated to include a Spartan III [Xilinx] based card with expanded capabilities.. Building on the knowledge and experience gathered from multiple IP and PMC BiSerial implementations and adding in the latest technology has created the PMC-BiSerial-III. The BiSerial III features completely isolated FIFOs with 32 bit ports for increased adaptability and performance. The [34] RS-485 / LVDS buffers have programmable termination, and direction control. Half-Duplex, Full-Duplex and single ended systems can be configured with software and VHDL. The denser, faster FPGA will implement the most complex state-machines. The prototype fabs are in test for the initial customer specific version; 32 Manchester channels with independent memories in one PMC.
7/2005 New Product Update: PMC-SpaceWire
Dynamic Engineering has delivered the first version of PMC-SpaceWire to three customers. The initial fab lot has been depleted. The design is being updated for ROHS and incorporation of design updates. The updated revision will be available late August / early September 2005. PMC-SpaceWire implements SpaceWire in a convenient PMC format. Utilize SpaceWire to communicate with the European Space Agency and NASA equipment utilizing the ECSS-E-50-12A specification. SpaceWire is configured using routers to create a heirarchical point-to-point system with high speed parallel paths. The SpaceWire specification calls for LVDS signaling and a 9 pin MDM connector. PMC-SpaceWire provides 4 SpaceWire attachments allowing your host to directly communicate with multiple devices. The hardware is supported with a Windows® driver. PMC-SpaceWire has been tested at 200 MHz. Test cables have been developed to meet the base requirements of SpaceWire - a good combination of capabilities and lower cost.
6/2005 Product Update Announcement: ROHS compliance
Dynamic Engineering has a plan in place to meet the ROHS requirements by the 2006 implementation deadline. Dynamic Engineering has decided to go with Gold instead of Tin for superior performance in the short and long term life of our product. Many of the components that we use already meet the ROHS requirements. When the rest of the components become available we will switch our process over to use ROHS compliant solder paste etc.
5/2005 New Product Announcement: PC/104p-BaseBoard
The BaseBoard is part of the PC/104 Module family of modular I/O components by Dynamic Engineering. The BaseBoard is used to integrate a PC/104p stack with the power supply, 35 Optocoupled Inputs, 37 Optocoupled Outputs, 2 UART - RS-485 ports, 2 ARINC 429 - TX/RX, 4 ADC Ports, and 4 DAC Ports comprize the onboard feature set of the BaseBoard design. The Right hand PC/104 slot is designed to be occupied by the Power Supply module which accepts 28V and supplies the standard PC/104 voltages on the ISA connector. The left hand slot is used to add a PC/104p stack.
4/2005 New Version Announcement: PMC-Serial-M1
Synchronous and Asynchronous programmable IO is provided by the PMC-Serial design. UART, HDLC, BiSync etc. are supported.
The PMC-Serial has been updated provide four RS-422 UART channels and no SCC
The FPGA supports the UARTs with write-through and pre-read capabilities plus data width control for
improved performance. The UARTs have 128 position FIFOs for each channel. Multiple on-board references are available to provide a multitude of operating
frequencies. Dynamic Engineering performed the design to support Mitre. The hardware is supported with an engineering kit.
4/2005 New Product Update: PMC-SpaceWire
Dynamic Engineering is under contract to make the first customerized version of PMC-SpaceWire. PMC-SpaceWire implements SpaceWire in a convenient
PMC format. Utilize SpaceWire to communicate with the European Space Agency and NASA equipment utilizing the ECSS-E-50-12A specification. SpaceWire
is configured using routers to create a heirarchical point-to-point system with high speed parallel paths. The SpaceWire specification calls for LVDS
signaling and a 9 pin MDM connector. PMC-SpaceWire provides 4 SpaceWire attachments allowing your host to directly communicate with multiple devices. The hardware
is supported with a Windows®; driver. PMC-SpaceWire has been tested at 200 MHz. PMC-SpaceWire is in final integration with customer equipment with first deliveries expected in the start of May/2005.
Test cables have been developed to meet the base requirements of SpaceWire - a good combination of capabilities and lower cost.
3/2005 New Product Announcement: BaseBoard
Dynamic Engineering is under contract with BAE to develop a specialized PC/104p „BaseBoard¾. The BaseBoard will have two PC/104 positions allowing a power supply module to be installed in one and a PC/104p stack to be installed in the other.
The BaseBoard acts as stack position 0 utilizing a Xilinx FPGA to interface with the PCI bus. BaseBoard has Optocoupled IO, UARTs, ARINC 429 ports, DAC and ADC ports. This is a quick turn project with delivery expected the first week of May 2005.
2/2005 New Product Announcement: cPCIBPMC3U64
Dynamic Engineering has completed the cPCIBPMC3U64 design. The Compact PCI carrier provides 1 PMC position on a 3U 4HP cPCI card. The configuration is intended for 64 bit cPCI backplanes. The bridge provides isolation from the backplane
allowing for 3.3 or 5V PMCs to be installed and to make adjustments in clock speeds. VIO is jumper selectable on the PMC side of the Bridge. There are options for connecting the Ethernet, Serial and I2C ports. IO is through the cPCI bezel.
Another version is coming soon which will have a 32 bit PCI bus and user IO to the rear panel.
1/2005 New Version Announcement: PMC-Serial-RTN5
Synchronous and Asynchronous programmable IO is provided by the PMC-Serial design. UART, HDLC, BiSync etc. are supported.
The PMC-Serial has been updated provide an option for RS-232 operation with the Serial Communications Controller, plsu 2 RS-232 and 2- RS422 channels on the UART.
The FPGA supports the UARTs with write-through and pre-read capabilities plus data width control for
improved performance. The UARTs have 128 position FIFOs for each channel. Multiple on-board references are available to provide a multitude of operating
frequencies. Dynamic Engineering performed the design to support Raytheon and the US Coast Guard. The hardware is supported with an engineering kit. A Windows driver is being written for the PMC-Serial-RTN5
12/2004 Updated Product Announcement: PCI-NECL-ASN1
The PCI-NECL-ASN1 supplies 20 ECL transmitters and 20 ECL receivers plus 12 TTL IO. The IO are supported with DMA and state-machine control plus a storage FIFO for data buffering. Custom frequencies can be programmed
into the PLL. The 20 inputs and outputs can be programmed to make parallel and serial interfaces. The spare IO can be used as a parallel port. PCI-NECL-ASN1
is a customerized version of the PCI-ECL card. Dynamic Engineering performed the design to a parallel interface. The hardware is supported with a Windows¨ driver. The driver and design are available as part of the engineering kit
to allow customers to create their own custom interfaces. The on-board FLASH is reprogrammable to support custom requirements.
11/2004 Driver available: PMC Parallel IO
The PMC Parallel IO is now supported by a WindowsÆ 2000/XP Compatible driver. The driver will decrease your time to market with direct access to the PMC Parallel IO hardware using standard C/C++ calls.
The PMC Parallel IO provides the common requirement of single ended IO for embedded systems. Each of the 64 IO are independently programmable for input and output. Front and rear panel IO are available. Interrupts are supported. Custom IO requirements are supported with a reprogrammable FPGA device.
10/2004 updated Design: PCI_Altera_485/LVDS
The PCI-Altera-485/LVDS has been updated to have the option to use a FLASH based PROM to load the Altera at power-up or to load from the Xilinx via software and the PCI bus. For applications requiring a quick start the PROM can configure the Altera before the OS is running. The PCI-Altera provides reconfigurable logic with a 20K400E plus DMA, 16 FIFOs, 8 triple PLLs, 12 TTL IO, and 40 RS-485 or LVDS IO.
10/2004 New Version Announcement: IP-HaveQuick is a new version of the IP-Parallel-HV
The HaveQuick version provides master and target capability to interface with TOD [time of day] equipment using the HaveQuick manchester encoded interface standard. As a target the time code from the TOD unit can be read by the host for an accurate time. The seconds, minutes, hours, days and years are encoded into the format. The IP-HaveQuick locally interpolates to provide a higher resolution time synchronized to the 1PPS [one pulse per second] reference and time code data. As a Master the hardware can be programmed with the start time and then run independently to provide a reference. The hardware is supported with an IP driver compatible with the Windows 2000Æ and XPÆ OS.
10/2004 New Version Announcement: PMC-BiSerial II-PS2 is a new version of the PMC-BiSerial II
The PS2 version provides eight serial channels and an 8 bit parallel port with RS-422/485 IO. The serial channels are configured with 4 transmit and 4 receive. The protocol provides a Data, Clock and Strobe interface. The transmit rate is programmable up to 20 MHz. Each channel [8] has a 128 x 32 FIFO for data storage. Lower cost version of the standard PMC-BiSerial product with smaller Block RAM FIFOs and more channels.
9/2004 New Product Announcement: cPCI4IP
The cPCI4IP provides four IndustryPackÆ slots in one 6U 4HP cPCI board. Use your favorite IP modules in a Compact PCI environment. The design supports 8,16,and 32 bit data transfers to 16 and 32 bit single and double wide IPs. IO, ID, Interrupt and Memory spaces supported. 8 and 32 Mhz operation in each slot. Fused filtered power to each slot. IO options for rear panel, front panel and both. Watchdog timer with bus error information per slot. WindowsÆ driver available.
9/2004 Updated Product Announcement: cPCI2IP
The cPCI2IP provides two IndustryPackÆ slots in one 3U 4HP cPCI board. Use your favorite IP modules in a Compact PCI environment. The updated design supports 8,16,and 32 bit data transfers to 16 and 32 bit single and double wide IPs. IO, ID, Interrupt and Memory spaces supported. 8 and 32 Mhz operation in either slot. Fused filtered power to each slot. IO options for rear panel, front panel and both. Watchdog timer with bus error information per slot. WindowsÆ driver available.
9/2004 New Version Announcement: PMC-Serial-RTN4
Synchronous and Asynchronous programmable IO is provided by the PMC-Serial
design. UART, HDLC, BiSync etc. are supported.
The PMC-Serial has been updated provde an option for RS-232 operation with
the Serial Communications Controller.
The L3 version is available with RS-485 IO on the SCC.
Both models have RS-232 IO for the QuadUART. The FPGA supports the UARTs
with write-through and pre-read capabilities plus data width control for
improved performance. The UARTs have 128 position FIFOs for each channel.
Multiple on-board references are available to provide a multitude of operating
frequencies. Dynamic Engineering performed the design to support Raytheon
and the US Coast Guard. The hardware is supported with an engineering kit.
8/2004 New Product Announcement: PCI-NECL-ASN1
The PCI-NECL-ASN1 supplies 20 ECL transmitters and 20 ECL receivers plus
12 TTL IO. The IO are supported with DMA and state-machine control plus
a storage FIFO for data buffering. Custom frequencies can be programmed
into the PLL. PCI-NECL-ASN1 is a customerized version of the PCI-ECL card.
The Interface has 16 bit parallel data with reference clock, data valid,
data ready, and buffer limit handshaking. Dynamic Engineering performed
the design to support Asine Ltd. The hardware is supported with a Windows¨
driver.
8/2004 New Product Announcement: PCI-NECL-XG1
The PCI-NECL-XG1 supplies 19 ECL transmitters and 19 ECL receivers
plus 12 TTL IO. The IO are supported with DMA and state-machine control
plus a storage FIFO for data buffering. Custom frequencies can be programmed
into the PLL. The 19 inputs and outputs can be programmed to make parallel
and serial interfaces. The spare IO can be used as a parallel port. PCI-NECL-XG1
is a customerized version of the PCI-ECL card. Dynamic Engineering performed
the design to support XG Technologies for a digital receiver interface
which operates at 170.6 MHz.. The interface is a 3 wire serial implementation
leaving 2 - 16 bit parallel ports. The hardware is supported with a Windows¨
driver.
7/2004 New Product Announcement: PMC-SpaceWire
Dynamic Engineering is under contract to make the first customerized
version of PMC-SpaceWire. PMC-SpaceWire implements SpaceWire in a convenient
PMC format. Utilize SpaceWire to communicate with the European Space Agency
and NASA equipment utilizing the ECSS-E-50-12A specification. SpaceWire
is configured using routers to create a heirarchical point-to-point system
with high speed parallel paths. The SpaceWire specification calls for LVDS
signaling and a 9 pin MDM connector. PMC-SpaceWire provides 3 SpaceWire attachements
allowing your host to directly communicate with multiple devices. The hardware
is supported with a Windows¨ driver.
6/2004 New Product Announcement: PCI-Serial_ECL
The PCI-Serial-ECL supplies 19 ECL transmitters and 19 ECL receivers
plus 12 TTL IO. The IO are supported with DMA and state-machine control
plus a storage FIFO for data buffering. Custom frequencies can be programmed
into the PLL. The 19 inputs and outputs can be programmed to make parallel
and serial interfaces. The spare IO can be used as a parallel port. Dynamic
Engineering is under contract to make the first customerized version of
the PCI-Serial-ECL for a digital receiver interface which operates at 170
MHz.. The interface is a 3 wire serial implementation leaving 2 - 16 bit
parallel ports. The hardware is supported with a Windows¨ driver.
6/2004 New Product Announcement: PC/104p-BiSerial
The BiSerial family has been expanded to include a PC/104p version
of the design. The new implementation builds on the PMC-BiSerial-II and
IP-BiSerial adding ADC and DAC capabilities. High speed programmable
FPGA for application specific state-machine implementations. 16 RS-485
transceivers which can be swapped with LVDS IO, 4 ADC [16 bit, 200 KHz.]
, 16 DAC [16 bit, 200 KHz] and 8 TTL make up the IO. Use for memory buffered
communications and control, hardware interface simulation, command and
control etc. BiSerial designs have been used for industrial control,
test support, simulation of other equipment, "glue" between incompatible
systems, communications, and more. Dynamic Engineering is under contract
to make the first customerized version of the PC/104p-BiSerial for a LASER
interface. The hardware is supported with a Windows¨ driver.
5/2004 Product Update Announcement:
PCI5IP-XP/2000
PCI5IP-XP/2000 is now available to support the Windows¨2000 OS.
The PCI5IP-XP/2000 driver is a "Parent" Driver for Windows¨XP or Windows¨2000
systems. The driver facilitates the integration of up to 5 IP modules
per PCI5IP and up to 10 PCI5IPs per system providing the kind of flexibility
that system designers need in todays fast changing high tech market place.
The driver is a purchase once and use many item - no additional royalties
etc. for same company use. The Driver and PCI5IP are stocked items.
3/2004 Product Update Announcement: PCI-Altera-485/LVDS
The PCI-Altera-485 has been updated to have a build option to install LVDS transceivers creating the PCI-Altera-LVDS. There are 40 transceivers on the card and the transceivers can be implemented with 485, LVDS or mixed. The 485 transceivers are rated for 40 MHz operation. The LVDS transceivers are rated for 200 MHz operation. In addition the PCI-Altera Windows¨ driver has been updated to support XP and 2000. The PCI-Altera is designed to accept user VHDL files and the generic driver allows the user to communicate with their custom implementation using standard C. Easy to install, easy to load, easy to use.
2/2004 New Product Announcement: PCI Cable adapter to support IP-Crypto
and IP-Tape
The Cable Assembly Crypto/Tape interconnects the IP Module Carrier
and the PCI Bezel via a connector board and and internal ribbon cables.
The IP-Crypto is broken out to an RJ45 and the IP-Tape to a SCSI connector.
The IP-Tape connector has additional pins for"self-healing" fused power
and ground.
2/2004 New Product Announcement: Single
Slot IP Module carrier for PC/104p applications
The PC104pIP lets you mount a an industrypack¨ module onto a
PC/104p in a standard PC/104p slot. The PC104pIP is based on the PC104p4IP
design and features 8/32 MHz IP clock selection, fused filtered power,
watchdog timer, 32 bit data handling, little/big endian support and more.
1/2004 New Design: PCI <-> PC/104p
adapter
The PCI2PC104p lets you mount a PC/104p devide in a standard PCI
slot. The PCI2PC104p has two configurations to support production and
test. Testpoints are provided for the PCI signals in the test configuration.
1/2004 New Design: Cable adapter
The IP-Crypto and IP-Tape are now supported with a cable adapter.
The cable adapter converts from ribbon cable [2 x 50] to RJ-435 and SCSI
III connectors. The RJ-45 has the IP-Crypto interface and the SCSI III
connector has 1:1 from the ribbon plus additional fused power and ground.
The SCSI connector can be used to support any IP.
1/2004 New Design: Windows¨XP and
2000 drivers for the IP Crypto.
The IP-Crypto drivers are "Child" Drivers used with a "Parent" driver
for the carrier the IP-Crypto is mounted to. For example with the PCI3IP the IP-Crypto can be installed into a standard
PCI slot and controlled with standard C software and Windows¨2000 or
XP operating systems. The IP-Crypto driver comes with source, example calling
program and documentation.
12/2003 New Design: PCI_Altera_485_XP
The PCI-Altera-485-XP driver is a "Parent" Driver for Windows¨XP
systems. The driver facilitates the operation of the PCI-Altera-485.
Multiple PCI-Altera-485's are supported per system providing the kind
of flexibility that system designers need in todays fast changing high
tech market place. The PCI-Altera-485 driver comes complete. The base
driver provides functionality to load the Altera with the user design,
recognize different Altera implementations and load the appropriate child
driver, and manage the PCI side of the design . The reference design [VHDL
and load file] provided with the driver supports the basic features on
the PCI-Altera-485 - PLLs, FIFOs etc.
11/2003 New Design: PMC-Serial
The PMC-Serial is an upgrade and replacement for the PMC-4U. The
PMC-Serial features up to 8 UART channels, an SCC, RS485, RS232, RS188,
RS423 options for IO. The standard configuration has 4 UART channels and
2 SCC channels. The UART is supported with 128 Deep FIFO per channel and
performance logic for effecient operation on the PCI bus.
11/2003 New Design: IP-BiSerial-Miller
The IP-BiSerial-MLR is what you need to connect your system to a
"Miller" encoded source and to transmit to another "Miller" encoded device.
The design features 16K bytes FIFOs, programmable interface rates, programmable
sync pattern, programmable frame length, programmable interrupts and more.
Miller encoding provides a 50% duty cycle [overall] data with embedded
clock interface. The encoding technique utilizes the time between transitions
to define the data. Ideal for telemetry and fiber applications. A Windows¨XP
driver is available.
10/2003 New Design: PCI3IP-XP
The PCI3IP-XP driver is a "Parent" Driver for Windows¨XP systems.
The driver facilitates the integration of up to 3 IP modules per PCI3IP
and up to 10 PCI3IPs per system providing the kind of flexibility that system
designers need in todays fast changing high tech market place. The PCI3IP-XP
driver comes complete with a generic IP driver to allow the use of IndustryPack¨
Modules that do not have an IP driver designed.
10/2003 Updated Design: PMC2PCI
The PMC2PCI by Dynamic Engineering integrates A PCI slot into a PMC
environment. Use your favorite PCI card with a PMC carrier. 32/33 and
64/66 operation. 3.3 or 5V IO. Now with a more efficient switching 3.3V
power supply design. User shunt to select PMC 3.3 or regulated 3.3.
Please look at the data page for a complete description.
9/2003 New Design: PC104p4IP
The PC104p4IP by Dynamic Engineering integrates your favorite IndustryPacks
with the PC/104+ module system. 4 IPs can be mounted to a single PC/104
slice. Fused filtered power on each slot, 8/16/32 bit operation with 16
and 32 bit IP modules, independent 8/32 MHz selection and more. Please look
at the data page for a complete description.
5/2003 New Design: IP-Pulse
The IP-Pulse by Dynamic Engineering solves your programmable pulse
generation requirements with 4 channels in a single IP Module. Each channel
is independent and can be programmed with the pulse width and time between
pulses. nS to seconds. The output pulses can be sent continuously or
for a pre-programmed count. The four channels can be synchronized or
started independently. Interrupt or polled operation.
5/2003 Updated Design: PCI3IP
PCI3IP-XP and Linux drivers coming soon! The PCI3IP by Dynamic Engineering
has been updated with an alternate user interface. The PCI3IP initializes
into the unifed (legacy) register set to support current installations.
The distributed register set is selected with a control bit in the base
register. The additional features will allow drivers written for the PCI5IP
to be ported to the PCI3IP and vice-versa.
5/2003 New Design: PCI5IP-XP
The PCI5IP-XP driver is a "Parent" Driver for Windows¨XP systems.
The driver facilitates the integration of up to 5 IP modules per PCI5IP
and up to 10 PCI5IPs per system providing the kind of flexibility that system
designers need in todays fast changing high tech market place.
5/2003 New Design: IP-BiSerial-NG4
Software programmable 3/4 wire modes, parity, transmit frequency,
the width of the synchronization pulse, the time delay after the sync and
the start of data, and the time between data words. The word transfer has
an associated Word Sync signal to provide for framing and error checking.
The Frame sync signal provides for message level synchronization. The Ng4
has programmable receive word count and receive all mode. The IP BiSerial
NG4 has a 50 MHz reference oscillator.
4/2003 New Design: cPCI2PMC
The cPCI2PMC ( cPCI to PMC ) cPCI2PMC
adapter / carrier converter card provides the ability to install a PMC
card into a standard cPCI slot. The cPCI2PMC has a PMC card slot mounted
to a universal 3U 4HP cPCI card. Suitable for 32/64 with 33/ 66 MHz bus
operation. The PMC user IO connector Pn4 is optionally connected to J2 for
rear panel IO. The PMC bezel connector is mounted though the cPCI mounting
bracket.
4/2003 New Design: cPCI2IP
The cPCI [CompactPCI] compatible cPCI2IP cPCI2IP
design adds 2 Industrypack compatible slots to your cPCI host. The cPCI2IP
acts as an adapter, converter, carrier, or bridge between the cPCI bus
and your IndustryPack hardware. The cPCI2IP is a 3U 4HP cPCI design with
2 IP slots.
3/2003 New version: IP-BiSerial-Q1
New version of the IP-BiSerial-IO designated IP-BiSerial-Q1 completed
for QinetiQ The IP-BiSerial-Q1 features 16
or 32 bit programmable data length plus parity, bursted clock with frequency
options and RS422 [RS485] IO.
3/2003 Updated Design: PCI3IP
The PCI3IP is now updated to be PCI 2.2 compliant and PCI universal
voltage. The updated version is a drop in replacement for the previous
PCI3IP revision. The PCI3IP features FAST¨
technology for high performance accessing your IndustryPack¨ modules.
2/2003 New Design: IP-OptoISO-16
16 Optically Isolated 0-60V 1.5A outputs - IndustryPack Product
now available for ordering. Please e-mail dedra@dyneng.com
1/2003 Design Award: IP-OptoISO-16
16 Optically Isolated 0-60V 1.5A outputs - IndustryPack Module design
awarded to Dynamic Engineering. Product available for shipping March
1, 2003. Please e-mail dedra@dyneng.com
1/2003 Developments: IP-OctalSerial
8 Channel Serial Data Interface IP Module shipped to customer. Please
e-mail dedra@dyneng.com
1/2003 Developments: IP-QuadUart-485
Customized version of the IP Quad UART ships to customer. Please
e-mail dedra@dyneng.com
8/2002 Contract Award: PMC-0C12
L3 Communications has awarded an new development contract to Dynamic
Engineering to create the PMC-OC12. The PMC-OC12 development will be
a quick reaction program to provide an OC12 capable fiber interface on
a PMC format card. The Agere "Ultramapper" will be utilized to provide
the protocol processing.
8/2002 -NG2 ships: IP-BiSerial-NG2
The IP-BiSerial update to create the IP-BiSerial-NG2 has been completed
and the hardware shipped.
7/2002 -S311 ships: PMC-BiSerial
The PMC-BiSerial-S311 Shipped to the customer and is now in integration
at their facility. The PMC-BiSerial-S311 was delivered with an NT driver
and PCI adapter to allow Northrop Grumman to interface to legacy radar
systems from a standard PC.
7/2002 Contract Award: PMC-BiSerial
BAE Systems has awarded an upgrade contract to Dynamic Engineering
to create the PMC-BiSerial-BAE1. The PMC-BiSerial-BAE1 will feature a
synchronous serial differential interface to a combination time distribution
network and control data. Independent transmit and receive channels.
7/2002 Contract Award: IP-BiSerial
Northrop Grumman Corp. has awarded an upgrade contract to Dynamic
Engineering to create the IP-BiSerial-NG2. The IP-BiSerial-NG2 will feature
a standard satelite interface [Frame Sync, Word Sync, Data and clock].
Independent transmit and receive channels. Programmable parity, length,
and data rates.
6/2002 Contract Award: PMC-BiSerial
Northrop Grumman Corp. has awarded an upgrade contract to Dynamic
Engineering to create the PMC-BiSerial-S311. The PMC-BiSerial-S311 will
be used with a PCI2PMC and Windows NT driver to provide an S311 interface
within a PCI chassis.
6/2002 Developments: PCI_Altera_485
Program your own Altera 10K200E or 10K130E from the PCI bus. 40
- 20 MHz. RS-485 IO and 12 TTL IO are provided via D100 connector for
IO. Spartan II and PLX 9054 provided to manage DMA on PCI bus. 16 - 4K
x 8 FIFOs between Altera and Xilinx. One 1K x 32 FIFO provided for DMA
optimization. Status - Schematic complete. Placement complete. Routing
in progress. ETA - July 2002. Boards will be supplied with base Altera
implementation, NT compatible loader software [for Altera] and preprogrammed
Xilinx.
5/2002 Developments: PCI3IP
PCI - Industrypack adapter - updated to have an optional minimized
memory map. The memory space was decreased to match the ID, IO, and INT
memory requirement. Only 2K bytes requried on the PCI bus. Prior purchased
hardware can be upgraded with our PROM upgrade program. Please e-mail
dedra@dyneng.com .
4/2002 Developments: IP-QuadUART
The IP-QuadUART provides 4 UART channels on a single IP card. The
channels are supported by 128 byte FIFOs and programmable RS-232 / RS-422
IO. Multiple baud rates are supported up to 2 MHz.
3/2002 Developments: PCI3IP
PCI - Industrypack adapter - updated to include new static and dynamic
address 32 <=> 16 bit data conversion [PCI <=> IP]. Prior
purchased hardware can be upgraded with our PROM upgrade program. Please
e-mail dedra@dyneng.com .
2/2002 Developments: PCI5IP
PCI - Industrypack adapter - Use a PCI card slot to mount your time
tested IP module designs. 5 IPs in one slot. 8/32 MHz selectable per
slot. Release date 3/15/02
1/2002 Developments: PMC2PCI
PMC - PCI adapter - Use a PCI card for development or production
in a PMC slot. Save time and money with existing PCI cards when a PMC
version is not available. In Stock
1/2002 Contract award: Embedded PC design: for special data
processing application. P3 with SDRAM, FLASH, Ethernet, local PCI, and
Xilinx based data filtering and control functions.
1/2002 Developments: pciBpmc
PCI Bridge PMC adapter - All of the benefits of our PCI2PMC design
plus a PCI bridge to allow multiple PMC's to be installed per PCI bus
segment. On board 7A 3.3V power supply, user selectable logic level [3.3
or 5V], Pn4 IO is accessible and PMC Bezel is mounted through the PCI
Bezel. In Stock
1/2002 Developments: IP-Compact Flash
IP-CompactFLASH - CompactFLASH to IP Module bridge. Meets IP electrical
and mechanical requirements. CompactFLASH connector on board. IO connector
pinned out for IDE interface to allow a second CompactFLASH or other compatible
hardware to be connected with a transition module. In stock.
11/2001 Developments: PCI LVDS 8T
PCI LVDS 8T : Dynamic Engineering successfully tests transmission
between 8T and 8R designs. 64 Mb of data was transmitted across 8 channels
simulataneously. The data was DMA transferred into the 8T, transmitted
to the 8R and then DMA transferred from the 8R back into host memory.
The received data was checked. The test was repeated in a loop with no
errors. The test was run for 24 hours. Development work continues on
the 8T driver and additional hardware testing. The second production order
for 40 of the 8R boards was received.
10/2001 Developments: PCI LVDS 8R
PCI LVDS 8R : Dynamic Engineering completes the PCI LVDS 8R. The
PCI LVDS 8R features 8 high speed LVDS channels which can receive and
store data into 512 mB of on board SDRAM. The data can then be moved to
host memory with scatter gather DMA. NT driver available. Custom digital
data filtering available.
07/2001 Developments: PMC BiSerial
Navy
PMC BiSerial Navy : Dynamic Engineering updates the PMC BiSerial
to perform Manchester encoding and decoding for a USN program. Redundant
transmit and receive channels
06/2001 Developments: PMC 4U
PMC 4U : Dynamic Engineering designs the PMC 4U to provide 4 UART
channels plus Z85C30 Serial Communications Controller. Multiple IO standards
supported including RS485, RS232, RS423, and RS188.
05/2001 Developments: PIM-Universal-IO
PIM-Universal-IO : Dynamic Engineering designs the PIM_Universal_IO
to facilitate rear panel IO in cPCI based systems using PMC's. The PIM_Universal_IO
provides the PMC front panel IO where rear panel IO is desired.
04/2001 Contract Award: PCI_LVDS_8T
PCI_LVDS_8T: Dynamic Engineering awarded 2nd design contract for
a PCI card with 8 channels of LVDS output, digital filtering and storage.
This board has up to 512 mb of SDRAM and scatter gather DMA capability..
..
04/2001 Product Release: PMC
PIM Module PIM modules now available for shipping
The PMC PIM's are 1/2 sized PMC cards mounted onto a PIM carrier board
to allow for rear panel I/O. The PIM's can be used with any PMC card.
This product can now be ordered through our sales office: sales@dyneng.com
(831) 336-8891.
03/2001 News from Dynamic Engineering
* Navy contracts with Dynamic Engineering for Manchester design.
* IP-Crypto KYK-13 interface completed
03/2001 New Product Release - IP
Parallel-BA1 "IP Tape"
Customer accepts protype - production units are in route to customer.
The IndustryPack compatible IP-Parallel-IO board adds 48 channels of
IO in one slot. Perfect for embedded control. All registers are read-writeable.
Mezzanine boards. This product can now be ordered through our sales office:
sales@dyneng.com (831) 336-8891.
View our other Industry Pack cards here: Industry
Pack cards by Dynamic Engineering
02/2001 Dynamic Engineering Design Awards:
* Contract awarded to design PIM module for Teraburst.
* Contract awarded to design PMC-4U
02/01 New Product Release - S_A_Relay
Allows undetectable active monitoring and data altering of two ethernet
(RJ-45) lines.
02/2001 New Product Release - IP
BiSerial-RTN2
RTN2 is an update to the IP Biserial-BA2 with an expanded word counter,
16 Mb FIFO, programmable parity odd/even and on/off, programmable almost
empty and programmable almost full interrupt capabilities added. IP, oscillator
or user clock reference with 12 bit programmable divider for transmit frequencies.
This product can now be ordered through our sales office: sales@dyneng.com
(831) 336-8891. View our other IP Biserials cards here: IP BiSerial versions by Dynamic Engineering
11/00 New Product Release - IP Parallel IO
IndustryPack compatible IP-Parallel-IO board adds 48 channels of
IO in one slot. Perfect for embedded control. All registers are read-writeable.
Mezzanine boards, VME, PCI, and custom architectures are supported. I/O
and embedded control are our specialties.
This product can now be ordered through our sales office: sales@dyneng.com
(831) 336-8891.
11/00 - Dynamic Engineering Design Awards:
* Contract to design specialized Parallel I/O IP [IndustryPack]
module.
* Network Physics awards contract to design ethernet relay bipass
card and offset PCI extender
* Raytheon awards contract to design modifications to our IP BiSerial
card.IP BiSerial
* Contract to design specialized BiSerial IP module with negative
voltage output.
Custom, IP, PMC, PC*MIP, PCI, VME Hardware,
Software designed to your requirements
11/00 - PCI2PMC Initial Production run
sells out in 30 days. The PCI2PMC adapter card allows the user to install
a PMC card into a standard PCI slot. Dynamic Engineering has experienced
exceptional response on this product and is currently accepting orders
for our next production run.
10/00 - PCI_LVDS_8R: Dynamic Engineering awarded design contract
for a PCI card with 8 channels of LVDS input, digital filtering and storage.
This board has up to 512 mb of SDRAM and scatter gather DMA capability....
9/26/00 - PCI2PMC released The PCI2PMC
adapter card allows the user to install a PMC card into a standard PCI
slot. The PCI2PMC has a PMC card slot mounted to a universal 1/2 length
PCI card. Suitable for 32 bit or 64 bit bus operation. The PMC user IO
connector Pn4 is brought out to two connectors for access (DIN IDC and SCSI
II compatible). The PMC front panel connector is mounted though the PCI
mounting bracket. For superior performance, the PCI bus is buffered with
10 ohm series resistors, clamped with Schotky diodes, and the PCI clock
is distributed with a zero delay buffer. The PCI2PMC design is passive
with no added delays to access the PMC hardware.
9/4/00 - PCI3IP updated A Watch Dog
timer function has been added to the PCI3IP design. The Watch Dog timer
will allow software to read from slots with broken or non-existent IPs without
hanging the PCI bus. Useful to find the top of memory, installed or not,
and protect against failures. The Watch Dog timer provides status and
an optional interrupt to the host to communicate the bus error condition.
7/11/00 - MacPortable Designs
Sold We have sold our Dynamic Engineering line of MacPortable Designs
to Houlton. Thank you for the many years of support our MacPortable
products. Please visit the Houlton page for continued service of your MacPortable
5/01/00 - New revision of BiSerial New
revision of BiSerial New version of BiSerial with 4 transmit channels.
Designed for Photo-Sonics.
4/01/00 - Design win awarded today from Lockheed for an IEEE extender
card re-design.
3/01/00 - Design win Awarded today from Entone - PCI based
ATM design featuring the Intel 80960RN, Fujitsu Firestream and PMC PHY,
128 Mb SDRAM, 4 Mb SRAM, FLASH, and a smart card reader.
2/25/00 - VME Interface Dynamic Engineering was awarded a
design contract by TRW for the design of a VME based telecommunications interface.
The VME [6U] ATM interface with E1 and E3 capabilities will feature a PMC-Sierra
PHY, Altera FPGA(s), and Dallas framers.
2/10/00 - PMC-BiSerial First shipment
of PMC-BiSerial hardware to SED Systems...14 units of the new design were
shipped to the customer today along with the PMC-BiSerial engineering kit.
2/1/00 - PMC-BiSerial Dynamic Engineering
Announces High Performance Differential Serial Interface Ben Lomond, CA,
February 2000 - Dynamic Engineering has announced the PMC-BiSerial-IO,
a high performance Bi-Directional Serial interface on a single-wide PMC module.
The PMC-BiSerial-IO is designed for embedded telecommunications, network
access, data communications and control applications that require high-speed
data throughput. The PMC-BiSerial-IO is available now.
The PMC-BiSerial-IO includes 16Kbytes of transmit and 16Kbytes of
receive FIFO which allows back-to-back transmission with minimum interface
latency. The memory is organized as 32 bit words. The State machines and
memory blocks are fully independent allowing concurrent transmission and
reception. The base design is optimized for long transmissions with programmable
interrupts based on FIFO capacity and transmission or reception completion.
The PMC-BiSerial-IO has 20 programmable differential transceivers with
programmable termination to support custom applications. PMC-BiSerial for more information.
Dynamic Engineering has been very successful with the IP-BiSerial
providing custom interface solutions to a wide variety of companies.
[ IP-BiSerial] Dynamic Engineering welcomes custom
interface requirements with the PMC-BiSerial-IO. The Xilinx FPGA is designed
to be customized quickly for specific customers needs. Dynamic Engineering
expects the -IO version to be the first of many implementations for the
PMC-BiSerial.
1/6/00 - New version of BiSerial released
[-LS1] New version of BiSerial with 4 Mhz Data, Clock, Strobe interface
16K FIFO. Designed for DERA / Land Systems
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