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Est. 1988


Dynamic Engineering's Industrypack Compatible Designs
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PCI5IP

PCI5IP is a full length universal voltage PCI card with 5 IP positions.
Shown With IP's Installed.

If you want to use IndustryPack® modules with your PCI system then the PCI5IP is the choice for you. The PCI5IP combines features you need with simplicity and speed. Up to 5 IP modules can be installed. 32 bit and double wide modules fit right in. Each slot has independent operation - control, clocking, IO, power filtering and protection. The PCI5IP is highly integrated with the PCI and IP interfaces closely coupled within the same FPGA. As a result the PCI5IP is faster, has a higher MTBF, and is easier to use than competing designs. There are fewer initialization steps and fewer PCI addresses to deal with and yet there are more features to work with. With the Windows®XP/2000 driver; operation can be plug and play.

Our customers are our best source of feed-back and new ideas to implement. The PCI5IP is now revision C for the PROM. The new features include Byte and Word Swapping, Bus error status for each slot independently, and 32 IP support. If you have PCI5IPs and want to update to the latest firmware we have a PROM update program. A minimal cost of $25 for the first updated PROM. Please provide your serial number(s) to be updated along with your PO.

Multi-board operation is supported. With multiple PCI5IPs in your system and unique cabling, sensors etc. for each slot on each PCI5IP it is important to know which PCI5IP is which and to properly control the IP modules mounted to them. A surface mount dip switch is provided to create a programmable identifier to the software. A specific PCI5IP can be matched up with the PCI address allocated to make for deterministic control. The switch can also be used for other purposes; configuration control or debugging for example. The switch values are available to be read via the PCI bus.

Each slot has a separate clock controller for 8 and 32 MHz operation. The clocks are locked together for the five slots plus the state-machine. Glitch free operation means the frequency can be be changed on the fly. Series and parallel terminations with equal length traces insure clean clocks and coherant operation across the 5 IPs and the controlling state-machine. A well designed clock distribution is critical for reliable operation.

Each slot has resettable self healing fused filtered power. +5,+12, and -12V supported.

Industry standard 50 pin [ribbon cable] headers are used with the IO connectors. Vertical connectors are provided in all positions. Ribbon cable or discrete wire cables can be interfaced directly with the PCI5IP. Alternatively the HDRterm50 can be used to create a terminal block interface.

Slots B/C and D/E are configured to accept two single IPs, or a double wide Industrypack compatible design. Slot A is available for single IPs. The data bus is designed to allow for 32 bit IP Bus operation. The data bus width is controlled by the address range the slot is controlled with. Automatic switching makes it possible to switch data bus size without changing the control registers for seamless operation.

Three methods of resetting the IPs are built into the PCI5IP. A local pushbutton reset switch is provided. The switch is accessible between slots C and D. The IPs can be reset from the control register within the FPGA via the software interface. The IPs are reset on power-up via a supervisory circuit that guarantees the 200 mS minimum reset requirement in the IP specification. The resets only affects the IP slots.

LEDs are provided to each of the five IP slots for activity indicators. When each slot is accessed the LED is flashed. The Xilinx provides a one shot circuit to stretch the on time to make it visable. Power indicator LEDs [3] are provided on slot C. An additional eight user LEDs are available for debugging or other purposes.

IndustryPacks are usually 16 bit devices and the PCI bus supports 32 bits. The PCI5IP accepts 32 bit PCI accesses and converts them into two 16 bit accesses with an auto-incremented or static address. One PCI access can be used to write to or read from two IP locations or twice to one location. Byte, Word and Long Word accesses are supported to the 16 and 32 bit IP sites from the PCI bus. If a 32 bit IP has been installed then direct 32 bit operation can be utilized.

The IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the PCI5IP is created. The PCI5IP responds normally to the host, not tying up the PCI bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have consequences. Multi-threaded software operation is supported with separate bus error status in each of the slot control registers.

The PCI bus is defined as little endian and many IPs have their register sets defined to operate efficiently with a little endian interface. The default settings on the PCI5IP are straight through byte for byte and D15-0 written to address 0x00 before D31-D16 written to address 0x02 when long words are written to 16 bit ports. Please note that any long word address can be used. The lower data is written to the lower address first, then the upper data to the upper address. Each slot has a ByteSwap and WordSwap control bit to allow Byte and Word Swapping to be performed to accommodate alternate IP and OS requirements.


Byte Swapping accesses to a 16 bit port.


Byte Swapping access to a 32 bit port


Connector positioning is compatible with IP-Debug-Bus to allow the user to isolate and debug the control interface of an IP. The IP-Debug-IO can be used in conjunction with the PCI5IP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.

PCI5IP Features

  • Size
    		•  Full size PCI card.


  • IP compatible slots
    		•  5 independent slots. Slots B/C and/or D/E can be used together for a double wide or 32 bit IP


  • Clocks
    		•  Each slot has independent selection of 8 and 32 MHz operation.


  • Access Width
    		•  Each IP Module slot can be accessed as byte, word, or long word. Long words are converted to double word accesses for 16 bit slots.


  • Bus Error
    		•  The Watch-Dog timer protects against PCI bus hangs by responding when the IP is not installed or has a failure. 7.3 uS timeout.


  • Cable interface
    		•  Industry standard 50 pin box header connectors. Vertical mount.


  • Software Interface
    		•  Control registers are read-writeable
    IO, ID, MEM, INT spaces supported. Windows XP, Windows 2000 and Linux drivers available.


  • Interrupts
    		•  Each IP has 2 potential interrupts. All 10 are routed to INTA on the PCI bus. Control registers are provided to determine the source of the interrupt


  • Power Requirement
    		•  +5V internally, +5V, +12V, -12V current determined by IPs installed


  • LEDs
    		•  +5V, +12V, -12V and activity LEDs. 8 user LEDs also available.


  • DIP switch
    		•  An 8 position switch is available to support multi-board operation or other user defined purposes.




    PCI5IP Benefits

  • Speed
    		•  With the direct PCI to IP Bridge design featured in the PCI5IP standard accesses to your hardware happen faster than in competing designs. Throughput is increased by an additional 50% when the 32 bit access mode is used. Fantastic for loading memory etc.


  • Price
    		•  The PCI5IP has the low price point.


  • Ease of Use
    		•  The PCI5IP is easy to use. A point and shoot user interface to the IP sites. Please download the manual and see for yourself. The engineering kit provides a good starting point for a new user.


  • Availability
    		•  The PCI5IP is a popular board. We keep the PCI5IP in stock. Send in your order and in most cases have your hardware the next day - delivered to you via FedEx.


  • Size
    		•  The PCI5IP is a full size PCI board which conforms to the PCI mechanical and electrical specifications. Eliminate mechanical interference issues. The plastic card guide extension is supplied with the PCI5IP.


  • IP Compatibility
    		•  The PCI5IP is IP compliant per the VITA 4 - 1995 specification. All Dynamic Engineering IP Modules are compatible with the PCI5IP. All other IP Modules which are compliant with the VITA specification can be expected to work.


  • PCI Compatibility
    		•  The PCI5IP is universal voltage, PCI compliant device. The PCI5IP can be expected to work in any PCI compliant backplane. The PCI5IP has been tested in multiple active and passive backplanes from Advantech, Dell, Intel, Apple Computer and other manufacturers. The PCI5IP has been tested in expansion chassis by SBS.

    Ordering Information

    PCI5IP
    PCI5IP-EJ - PCI5IP with Ejector Style Header connectors

    To include a Driver and/or Hardware Engineering kit with your order please select from below.

    Quantity



    Engineering Kits

    Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. We recognize that different customers have different needs. The Engineering Kits are standardized in description to help with selection. The kits are segmented to allow for customers who only need hardware support, software support or a mixture. The Engineering Kit is highly recommended for first time buyers. The kit pricing is discounted to encourage their use.

    PCI5IP-Eng-1 ..........Hardware Support Engineering Kit includes:
    Board level Schematics [PDF], IP-Debug-Bus, IP-Debug-IO.
    PCI5IP-Eng-2 ..........Hardware Support plus Driver Engineering Kit includes:
    Board level Schematics [PDF], Software[PCI5IP Driver and sample application zip file ], IP-Debug-Bus, IP-Debug-IO.
    PCI5IP Drivers .......... Software Support Only Win®XP & 2000 compliant drivers for the PCI5IP:
    PCI5IP-XP/2000 Win®XP & 2000 driver for PCI5IP. The driver is designed to be overlayed with individual IP Module(s) driver(s). Please see the Driver manual for the specifics of writing your board interface. Please contact Dynamic Engineering if you would like us to produce one for your IP or a third party design.
    PCI5IP-LINUX Driver for PCI5IP: The driver is designed to be overlayed with individual IP Module(s) driver(s). Please see the Driver manual for the specifics of writing your board interface.


    Please select between the Linux and Windows drivers for your engineering kit. Please refer to the individual IP pages for driver availability. We are working on drivers for most of our IPs. You can influence the order in which we complete them. Please let us know which ones you need first! Please contact Dynamic Engineering if you would like us to produce a driver for your IP or a third party design.


    PCI5IP is a full length universal voltage signaling PCI card with 5 IP slots front view.



    Manuals

    Download the PCI5IP revision C Manual 7/6/03 in PDF format.
    Download the PCI5IP XP/2000 Driver Manual in PDF format.
    Download the Generic IP Driver Manual in PDF format. Win®XP & 2000 Generic driver for PCI5IP when a custom IP driver is not available. The generic driver is included with the PCI5IP-XP/2000 driver along with a sample user application making calls to the generic driver and an IP-Parallel-TTL.
    Download the PCI5IP Linux Driver Manual 8/1/03 in PDF format.


    Related Products

    PCI5IP Driver
    Win®XP & 2000 Drivers for PCI5IP


    PCI5IP-LINUX Driver
    Driver is designed to be overlayed with individual IP Module(s) driver(s)


     IP-DEBUG-IO II
    IP IO Connector Break-out Adapter


    IP-DEBUG-BUS
    IP module extender specialized for debugging


    HDRterm50
    50 position terminal block with ribbon cable connector


    HDRribn50
    Ribbon Cable for IP Modules with strain relief and cable pull tab


    IP-MTG-KIT
    Mounting Hardware for IP Modules






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