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Est. 1988


Dynamic Engineering's Industrypack Compatible Designs

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    • PCI3IP

    3 slot PCI IP Carrier, PCI IP Adapter, PCI IndustryPack® carrier, PCI IndustryPack® Adapter for IP modules

    The PCI compatible PCI3IP design adds 3 IndustryPack® compatible slots to your PCI host. The PCI3IP acts as an adapter, converter, carrier, or bridge between the PCI bus and your IndustryPack® hardware. The PCI3IP is a half size PCI card with 3 IP sites; compatible with the smallest chassis and the tallest processors that prevent full size solutions. Windows® and Linux drivers available.

    Each slot has a separate clock controller for 8 and 32 MHz operation. The clocks are locked together with a PLL, allowing glitch free operation, and the frequency to be changed on the fly.

    Each slot has resettable fused filtered power. The power is distributed with separated power planes to provide isolation between the slots.

    Industry standard 50 pin [ribbon cable] headers are used with the IO connectors. Vertical connectors are provided in all positions. Ribbon cable or discrete wire cables can be interfaced directly with the PCI3IP. Alternatively the HDRterm50 can be used to create a terminal block interface.

    Slots A and B are configured to accept two single IPs, or a double wide Industrypack compatible design. Slot C is available for single IPs.

    A local reset switch is provided for the IP boards. In addition the IPs can be reset from the control register within the Xilinx via the software interface.

    LEDs are provided to each of the three IP slots for activity indicators. When each slot is accessed the LED is flashed. The Xilinx provides a one shot circuit to stretch the on time to make it visible. Power indicator LEDs are provided on slot A. An additional six user LEDs are available for debugging or other purposes.

    A surface mount dip switch is available for configuration control or debugging purposes. The switch values are available to be read via the PCI bus.

    IndustryPacks are 16 bit devices and the PCI bus supports 32 bits. The PCI3IP accepts 32 bit PCI accesses and converts them into two 16 bit accesses. The IP accesses can be auto-incremented or static address accesses. With the static access option the upper or lower word can be accessed twice. With auto-incremented addresses both words are read from or written to. One PCI access can be used to write to or read from two IP locations. Our customers have measured a 50% speed improvement from the use of the long word access to the IPs. Byte, Word and Long Word accesses are supported to the IP sites from the PCI bus.

    The IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the PCI3IP is created. The PCI3IP responds normally to the host, not tying up the PCI bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have consequences.

    Connector positioning is compatible with IP-Debug-Bus will allow the user to isolate and debug the control interface of an IP. The IP-Debug-IO can be used in conjunction with the PCI3IP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.

    The PCI3IP has an alternate "mini-map" option available. The standard design provides the full address space to the IP Memory space. The mini-map provides a minimized memory space equal to the ID, IO, and INT spaces with 128 bytes. The total PCI memory space is reduced to 2K with this option. Please download the alternate manual to get the address map and other details. Please order with the -MM option for the mini-map.

    PCI3IP Features

  • Size
    		•  Half size PCI card.

  • IP compatible slots
    		•  3 independent slots. Slot A and B can be used together for a double wide IP

  • Clocks
    		•  Each slot has independent selection of 8 and 32 MHz operation.

  • Access Width
    		•  Each slot can be accessed as byte, word, or long word. Long word accesses can be static or auto-incrementing to the IP slot.

  • Bus Error
    		•  The Watch-Dog timer protects against PCI bus hangs by responding when the IP is not installed or has a failure. 7.3 uS timeout.

  • Cable interface
    		•  Industry standard 50 pin box header connectors. Vertical mount.

  • Software Interface
    		•  Control registers are read-writeable
    IO, ID, MEM, INT spaces supported.
    Windows® and Linux Drivers available

  • Interrupts
    		•  Each IP has 2 potential interrupts. All 6 are routed to INTA on the PCI bus. Control registers are provided to determine the source of the interrupt

  • Power Requirement
    		•  +5V internally, +5V, +12V, -12V current determined by IPs installed

  • LEDs
    		•  +5V, +12V, -12V and activity LEDs. 6 user LEDs also available.

  • DIP switch
    		•  An 8 position switch is available to allow for configuration control, or to facilitate debugging, and to provide a positive ID of each PCI3IP in your system

  • Reliability
    		•  1.322 million hours. Bellcore. GB 25c


    PCI3IP Benefits
  • Speed
    		•  With the direct PCI to IP Bridge design featured in the PCI3IP the access to your hardware happens faster than in competing designs. The 32 bit access capabilities further extends the lead in speed. Our customers report a 50% improvement using the 32 bit access feature compared to not using it on the PCI3IP.

  • Price
    		•  The PCI3IP has the low price point. Why pay for slots you are not using?

  • Ease of Use
    		•  The PCI3IP is easy to use. A point and shoot user interface to the IP sites. Please download the manual and see for yourself. The engineering kit provides a good starting point for a new user.

  • Availability
    		•  The PCI3IP is a popular board. We keep the PCI3IP in stock. Send in your order and in most cases have your hardware the next day - delivered to you via FedEx.

  • Size
    		•  The PCI3IP is a half size PCI board which conforms to the PCI mechanical and electrical specifications. Eliminate mechanical interference issues. The PCI3IP can be used in all PCI slots including the new narrow chassis.

  • IP Compatibility
    		•  The PCI3IP is IP compliant per the VITA 4 - 1995 specification. All Dynamic Engineering IP Modules are compatible with the PCI3IP. All other IP Modules which are compliant with the VITA specification can be expected to work. ID, IO, INT, and Memory spaces are supported in all 3 positions. The -MM option reduces the overall PCI address space requirement for those designs not using the full IP Memory space.

  • PCI Compatibility
    		•  The PCI3IP is a universal voltage, PCI compliant device. The PCI3IP can be expected to work in any PCI compliant backplane. The PCI3IP has been tested in multiple active and passive backplanes from Advantech, Dell, Intel, Apple Computer and other manufacturers. The PCI3IP has been tested in expansion chassis by SBS.


    Ordering Information

    PCI3IP

    To include a Driver and/or Hardware Engineering kit with your order select from below.

    Quantity


    Engineering Kits

    Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. We recognize that different customers have different needs. The Engineering Kits are standardized in description to help with selection. The kits are segmented to allow for customers who only need hardware support, software support or a mixture. The Engineering Kit is highly recommended for first time buyers. The kit pricing is discounted to encourage their use.

    PCI3IP-Eng-1..... Hardware Support Engineering Kit includes: Board level Schematics [PDF], IP-Debug-Bus, IP-Debug-IO.

    PCI3IP-Eng-2..... Hardware Support plus Driver Engineering Kit includes: Board level Schematics [PDF], Software[PCI3IP Driver and sample application zip file ], IP-Debug-Bus, IP-Debug-IO.

    PCI3IP Drivers..... Software Support Only PCI3IP Windows®XP/2000 or Linux compliant drivers:
    PCI3IP-XP/2000 Windows®XP/2000 or Linux drivers for PCI3IP. The driver is designed to be overlayed with individual IP Module(s) driver(s). Please see the Driver manual for the specifics of writing your board interface. Please contact Dynamic Engineering if you would like us to produce one for your IP or a third party design. Please select between the Linux and Windows drivers for your engineering kit.

    Manuals

    Download the PCI3IP Manual 4/2/04 in PDF format.
    Download the PCI3IP mini-map Manual 5/22/02 in PDF format.
    Download the PCI3IP-XP/2000 Driver Manual in PDF format.
    Download the Generic IP Driver for Windows® Manual in PDF format.
    Download the Carrier Group Linux Manual in PDF format.
    Download the Generic IP Driver for Linux Manual in PDF format.

    Use the Generic driver when a custom IP driver is not available. The generic driver is included with the PCI3IP-XP/2000 and Linux drivers along with a sample user application making calls to the generic driver and an IP-Parallel-TTL.

    Please refer to the individual IP pages for driver availability. We are working on drivers for most of our IP´s. You can influence the order in which we complete them. Please let us know which one you need first!

    Please contact Dynamic Engineering if you would like us to produce one for your IP or a third party design.


    Related Products


    PCI3IP Driver Win®XP & 2000 Drivers for PCI3IP
    IP-DEBUG-IO II IP IO Connector Break-out Adapter
    IP-DEBUG-BUS IP module extender specialized for debugging
    HDRterm50 50 position terminal block with ribbon cable connector
    HDRribn50 Ribbon Cable for IP Modules with strain relief and cable pull tab
    IP-MTG-KIT Mounting Hardware for IP Modules


    Custom, IP, PMC, cPCI, PCI, PC*MIP, VME Hardware, Software designed to your requirements

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