PCI-Altera-485
PCI-Altera-LVDS
Front view of PCI Altera


Rear view of PCI Altera



PCI Altera 485/LVDS comes with everything you need to load your Altera program into the 20K400E. Fantastic for development, simulation, special purpose interfaces, multiple serial and / or parallel channels.

The PCI compatible PCI-Altera-485/LVDS design is for the advanced user who wants to implement their own Altera design or requires reconfigurable logic. The PCI-Altera-485/LVDS makes the implementation and use of the 20K400E easy. Larger Altera parts are available.

The design comes with the basic features built in and the specific features ready for you. The PLX9054 and Xilinx take care of the PCI interface for initial loading of the Altera, and DMA transfer of data into and out of the FIFOs. The Altera controls 40 programmable RS-485 or LVDS transceivers and 12 TTL IO. Each of the RS-485 or LVDS channels is programmable for direction, termination and function. The 12 TTL IO can be inputs or outputs. Eight Cypress 22393 PLLs support the Altera providing the ability to synthesize multiple reference rates. The only thing missing is your input in the form of a coprocessor, reconfigurable logic, state-machine, simulated system, asynchronous or synchronous data processing etc.

The PLX 9054 provides a 33/32 PCI interface with bus master capabilities. The 9054 and Xilinx are used to move data to the Altera for output channels and to move data to the host for input channels. 8 input and 8 output FIFOs are provided to support 8 bi-directional channels. The intermediate FIFOs are byte wide. The PCI bus is 32 bit oriented. A 1K x 32 FIFO is used to convert the byte wide data to long word prior to DMA or post DMA depending on the direction of data transfer. The 16 intermediate FIFOs have programmable flags which can be used to cause interrupts for flow control.

IO is accomplished via RS-485 or LVDS transceivers or TTL buffers. The RS-485 transceivers are rated for 40 MHz. The LVDS is rated for 200 MHz. Each transceiver can be controlled for direction and termination. The TTL IO is implemented with ´125 open drain drivers with on-board pull-ups. The input direction is buffered with a receiver to protect the Altera and to provide level shifting between the 5V IO and the 3.3V Altera IO. The D100 [ SCSI II 100 pin connector ] provides an easy to interconnect cabling system. The pinouts are consistent with the industry standard differential pairings. The HDEterm100 supports the D100 with a cable to terminal strip conversion.

An 8 position dip switch is provided. The switch is read through the Xilinx. The switch can be used to distinguish multiple PCI_Altera_485 boards in the same system or for other user determined purposes. In addition a pair of shunts is provided on the Altera which can be used to select modes or for any other user defined purpose.

Six LEDs are provided. One is controlled via the Xilinx and can be used for any user purpose. A second LED is for 3.3V regulator power status and the last 4 are controlled via the Altera and the user design. The LEDs can be used for debugging or for system status etc.

The PCI clock is buffered with a zero delay buffer. The PCI side of the PLX 9054 is connected with the PCI required trace length. The clock signal is buffered with 3805 clock drivers and controlled length terminated clock distribution. The local side of the PLX, Xilinx, both sides of the 1K x 32 FIFO, Altera, the input side of the TX FIFOs, and the output side of the RX FIFOs are provided the distributed clock. All of the clocks and pulsed control signals are terminated with series at the source and parallel at the destination, and length matched for clean and coherent clock distribution and control. The Altera driven and read sides of the FIFOs are provided clocks and controls from the Altera for maximum user control. The PLLs can be used to create the local references. The signals are terminated with 22 ohms at the source and 1K pull-up at the FIFO. The FIFOs can provide rate matching between the Altera interface "native" speed and the PCI speed.

The PCI Altera design has been upgraded several times based on customer requests for new features. The LVDS and most recently the PROM addition are examples. With the PROM the user can pre-load the Altera during the power on sequence. The PROM is FLASH based and can be reprogrammed via the supplied JTAG header. A shunt can be used to select between the PROM and the Xilinx as the source of the Altera programming file. Revision F and later have the option to install the PROM. Revision G and later have one additional feature which is to be able to load from the PROM and later load from the Xilinx under software control. With Revision F the shunt selects one or the other. With Revision G the shunt selects the initial load after power up.

Software [Windows® driver] to load the Altera, access the hardware, and run diagnostics is available as well as a reference design for the Altera which controls the IO, PLLs and Altera side of the FIFOs. We provide a plug ´n play set-up along with our ATP software to give you a running start at your design. We have done several implementations to help our customers. If you need the features of the PCI-Altera-485/LVDS and prefer to have someone else do the programming, please contact us with your requirements.

New version now available - Use the "Plus Size" version to do your more intense designs. 20K600, double density intermediate FIFO´s and larger Block RAM in the Xilinx add-up to more gates and more throughput for "more faste" operation.



PCI Altera 485/LVDS Features

Size	Small size PCI card.
Altera	20K400E in BGA652 package standard. Larger parts are available upon request.
Clocks	PCI clock is distributed to the PLX, Xilinx, Altera, and "PCI side" of FIFOs. 66.666 MHz reference oscillator connected to Altera. 8 Cypress 22393 PLL´s are controlled by the Altera for additional clocking options.
PCI Bus	33 MHz 32 bit PCI bus implementation with DMA.
Cable interface	D100 connector provided with differential pinouts.
IO	40 - 40 MHz. capable RS-485 or 40-200 MHz LVDS plus 12 TTL IO are provided.
Software Interface	Control registers are read-writeable. Xilinx provides mechanism to download Altera implementation.
Interrupts	Multiple programmed interrupts are routed to INTA. Status register provided to determine cause of interrupt. Polled operation with interrupt masked.
Power Requirement	+5V only. 3.3, 2.5, and 1.8 produced by on-board regulators
LEDs	5 user LEDs also available.
DIP switch	An 8 position switch is available to allow for configuration control or to facilitate debugging
MTBF	463,775 Hours Bellcore SR332 MTBF
Humidity	The PCI-Altera-485/LVDS is a standard commercial grade board, able to handle the usual 10-90% non-condensing humidity rating. If you need to have a board used in a more harsh environment, ask to have humi-seal after final test.

PCI-Altera-485/LVDS Benefits

Speed	Direct DMA access to the hardware using the industry standard PLX 9054. 40 MHz RS-485 or 40 - 200 MHz LVDS. 16 rate matching FIFOs for full support of 8 bi-directional serial or parallel data channels. Altera 20K400EBC652-3. [larger parts and different speed grades are available by special order] The hardware can sustain high speed operation on multiple IO channels.
Price	The PCI-Altera-485/LVDS is a generic board which can be shaped for your needs. It is off-the-shelf and much lower cost than developing your own PCB, loader software etc. Quantity discounts are available making it the way to go for your production requirements too. Once your implementation is "nailed" then we can do a specific version for you with minimized or expanded features.
Ease of Use	The PCI-Altera-485/LVDS is easy to use. Just plug in and download your implementation. The engineering kit comes with support to load the Altera, and run basic tests on the hardware, break-out box and cable.
Availability	The PCI-Altera-485/LVDS is available. All functions are fully operational. The design is an off-the-shelf product.
Size	The PCI-Altera-485/LVDS is a half size PCI board which conforms to the PCI mechanical and electrical specifications. Can be used in all PCI slots including the half-size industrial chassis.
PCI Compatibility	The PCI-Altera-485/LVDS is PCI compliant. The PCI_Altera can be expected to work in any PCI compliant backplane. The PCI_Altera has been tested in multiple PC systems from various manufacturers.

Front view of PCI Altera PLUS

Rear view of PCI Altera PLUS

Ordering Information
PCI-Altera-485.............................485 IO version
PCI-Altera-485PLUS................485 IO version with 20K600 Altera, double density FIFOs and larger Xilinx
PCI-Altera-485-1........................Alternate verticle connector installed for internal wiring
PCI-Altera-LVDS.........................LVDS IO version
PCI-Altera-LVDSPLUS.............LVDS IO version with 20K600 Altera, double density FIFOs and larger Xilinx
PCI-Altera-LVDS-1.....................LVDS version with alternate verticle connector
PROM...............................................suffix to add if the PROM option is required

To include a Driver and/or Engineering kit w/order select Please select card version: 485, LVDS, mixed

To include a Driver and/or Engineering kit w/order select Please select card version: 485, LVDS, mixed

Select card version PCI-Altera-485 PCI-Altera-485(full featured card) PCI-Altera-485-1: PCI-Altera-LVDS PCI-Altera-LVDS-1 PCI-Altera-1/2 485,1/2 LVDS PCI-Altera-LVDS-PLUS PCI-Altera-485-PLUS No Engineering Kit Add: Hardware Engineering kit (PCI Altera Eng-1) Add:PCI-Altera-Eng-2 HW Support & Driver Add: Software Support Only
Quantity

PCI-Altera-mixed................Mix the LVDS and 485 IO. The standard 485 are 5V parts and the LVDS is 3.3. When used in the mixed mode the 485 parts will be replaced with 3.3V devices. The 3.3V devices [485] have less bandwidth than the 5V. Please contact the factory to provide the channel counts that you require. A new -# will be created for your version.


Engineering Kits

Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. We recognize that different customers have different needs. The Engineering Kits are standardized in description to help with selection. The kits are segmented to allow for customers who only need hardware support, software support or a mixture. The Engineering Kit is highly recommended for first time buyers. The kit pricing is discounted to encourage their use.

PCI-Altera-485/LVDS-Eng-1 .......... Hardware Support Engineering Kit includes:
Board level Schematics [PDF], HDETerm100, HDECable100, and Altera Reference design [VHDL]
PCI-Altera-485/LVDS-Eng-2 .......... Hardware Support plus Driver Engineering Kit includes:
Board level Schematics [PDF], Software[Driver and sample application ], Altera Reference design [VHDL], HDETerm100 and HDECable100
PCI-Altera-485/LVDS Drivers.......... Software Support Only Windows®XP and 2000 compliant drivers for the PCI-Altera-485/LVDS: Driver and user application.


PCI-Altera-485-XP/2000 simplified block diagram of Parent Child Hardware relationship.
Click on diagram for XP/2000 data page


Manuals
Download the PCI-Altera-485/LVDS Manual rev H4 in PDF format.

Download the Application note describing update to TTL output section in revision H boards in PDF format.

Download the PCI-Altera-485/LVDS XP/2000 Driver Manual rev D in PDF format.

Download the PCI-Altera-485/LVDS XP/2000 Generic Interface Manual rev C in PDF format.

Download the PCI-Altera-485/LVDS ATP implementation driver Manual rev C in PDF format.

Download the PCI-Altera-485/LVDS FM1 implementation driver Manual rev A in PDF format. Customer specific implemetation of VHDL and driver.

Download the PCI-Altera-485/LVDS FM1Manual rev A in PDF format. Customer specific implemetation of VHDL and driver.

Download the PCI-Altera-485/LVDS CSC implementation driver Manual rev A in PDF format. Customer specific implemetation of VHDL and driver.


Block diagram of VHDL design included with Hardware Support Engineering Kit.

The VHDL source code for the design shown in the block diagram is included in the Hardware Support Engineering Kit. The design is a good starting point for many user designs. The design includes all of the basics that you will need : Bus interface to PCI side logic, memory interface to FIFOs, PLL, TTL, and Differential IO, termination and direction control. Dynamic Engineering uses this design along with the driver and Userap.exe program [source for Userap.exe included in Software support Engineering kit] to test the PCI-Altera design. The downloadable VHDL user manual has more information to help with your modifications and design effort.

Download the PCI-Altera-485/LVDS ATP implementation VHDL Manual rev A in PDF format.

Download the CyberClocks R2.01.00 software
right click on the above link to download and save the cyberclocks zip folder to your target



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