150 DuBois St. Suite #3
Santa Cruz, Calif. 95060
(831) 457 8891 (831) 457 4793 Fax
Est. 1988


Dynamic Engineering's PCI Compatible Designs

PCI-ECL

PCI-ECL has a high speed PCI interface with DMA to support the ECL and TTL IO


Do you feel the need for speed? Differential ECL / NECL is still the interface of choice for high speed in noisy environments. PCI-ECL is a general purpose design with ECL and TTL IO plus a high speed Xilinx Virtex II Pro to control it. NECL, LVPECL and other ECL translators can be installed to meet IO requirements.

PCI-ECL features a PLX PCI interface chip with DMA support coupled with a Virtex II Pro device to support your design requirements. Dynamic Engineering can design a solution for you or you can implement one too. The Xilinx is reconfigurable, and supported with reprogrammable FLASH. The reference design contains the interfacing to the PLX with DMA support, FIFO, IO and PLL. The reference design is supported with a Windows® driver which has the capability to support your changes without having to write a new driver. We can of course make a new driver with direct calls to your hardware design implementation.

The ECL IO is carefully routed to provide 100 ohm differential impedance, and matched length from the pin edge on the D100 connector to the Xilinx [BGA] Ball. All of the TX are matched and all of the RX are matched to allow for high speed designs with tight timing requirements. One ECL input bit is tied to a clock capable input pin on the Xilinx to allow for an external reference clock.

The Xilinx is supported by a programmable PLL. The PLL is programmed with a serial bus via the Xilinx control register set. The Windows® driver handles this function. We recommend using the Cypress calculator to determine the PLL settings. The PLL supplies three clocks to the Xilinx which can be used for custom state-machine support. The clocks are received on dedicated clock pins.

In addition to the PLL a customer selected oscillator position is supplied. The oscillator can be used if an exact frequency match is required which can't be synthesized with the PLL using the PCI clock as a reference. The base design uses a PCI doubled rate of 66 MHz as the reference for the PLL.

The ECL section has 20 inputs and 20 outputs. The state-machine can be programmed to use any number of the IO.. The remaining IO can be used for a general purpose parallel port. Serial and Parallel interfaces can be implemented. For example, with a 4 wire serial interface a 16 bit parallel port will be available.

The external FIFO is used to store data from reception or for transmission. The FIFO is large enough that the IO can operate without interruption. The system can go away for up to 24 mS with a 170 MHz serial data stream and not under or over flow the memory.

The Internal FIFO is to support DMA. The data is pipelined into or out of the FIFO under control of the scatter gather DMA engine. Data can also be moved with non DMA read or write operations. Data stored into the FIFO is moved to the external FIFO and vice-versa. A state-machine moves the data with a burst transfer when there is sufficient data to move and single transfers when near the boundary conditions. The state-machine for the data transfer operates autonomously.

Multi-board operation is supported. With multiple PCI-ECLs in your system and unique cabling, sensors etc. for each slot it is important to know which PCI-ECL is which. A surface mount dip switch is provided which provides an identifier to the software. A specific PCI-ECL can be matched up with the PCI address allocated to make for deterministic control. The switch can also be used for other purposes; configuration control or debugging for example. The switch values are available to be read via the PCI bus.

The reprogrammable FLASH memory stores the Xilinx design file. The JTAG header is used to load the FLASH using the Xilinx standard IMPACT® software and parallel download cable.

PCI-ECL can be ordered with a standard IO control design or updated with a customer specific design via the FLASH. If you prefer to design your own interface; the -ASN1 version HTML is available as part of the engineering kit. When Dynamic Engineering creates a new design the new design is named PCI-ECLSTANDARD-Customernamedesignnumber. For example the PCI-NECL-XG1 is the first NECL based version done for the XG company. The new design will be fully documented and the manual available from this web page. Dynamic Engineering is available to engineer customer specific solutions using PCI-ECL and other Dynamic Engineering designs. Please contact engineering@dyneng.com or call and ask to speak with one of our knowledgeable technical sales staff to help you with your implementation requirements.

The IO is brought to a D100 connector. The connector on the PCI-ECL is a available in the standard right angle or a vertical mount. The right angle connector mounts through the bezel allowing for IO outside of the chassis. The vertical connector is used with a blank bezel and is optimized for internal to the chassis IO requirements. The mating connector is the AMP 749621-9 or 719109-7. Dynamic Engineering has cables and a break-out for this connector. HDEterm100 can be used to create a terminal block interface. HDEcabl100 is the standard cable. Customer specific cables can be manufactured. Please forward your connector and pin assignment requirements if you are interested in custom cables. In addition Dynamic Engineering has a "cross over" cable which can be used to interconnect two PCI-ECL cards or to connect to your equipment if you adopt the connector definitions that we used. The Pinouts are available within the manuals.

An LED is provided under the control of the Xilinx. The user can determine the purpose for the LED. It is an effective tool for identifying the board being accessed, debugging software, providing status and so forth. Sometimes your customers may just like to see that the electronics are doing something.


Block Diagram of PCI-ECL


PCI-ECL Features

  • Size
    		•  1/2 size PCI card.


  • IO
    		•  20 ECL TX, 20 ECL RX, 12 TTL IO.


  • Clocks
    		•  PLL [Cypress 22393], PCI, OSC, External clock sources are available for use


  • Xilinx
    		•  Virtex II Pro '04'


  • PCI Bus
    		•  33 MHz 32 bit PCI bus implementation with DMA. Universal Voltage keying.


  • Cable interface
    		•  D100 connector. Pinout in manual. Right angle standard, Vertical mount available.


  • Software Interface
    		•  Control registers are read-writeable. Windows® XP/2000 drivers available.


  • Interrupts
    		•  Multiple status and operation based programmable interrupts are provided. FIFO almost empty, FIFO almost Full, transmit complete, receive complete etc.. All are routed to INTA on the PCI bus. Control and status registers are provided to control and to determine the source of the interrupt


  • Power Requirement
    		•  on board power supplies create +3.3, +2.5, +1.5, and -5V. Shunt option to use backplane or on-board 3.3V power.


  • LEDs
    		•  +3.3V and user LEDs available.


  • DIP switch
    		•  An 8 position switch is available to support multi-board operation or other user defined purposes.


  • Humidity
    		•  The PCI-ECL is a standard commercial grade board, able to handle the usual 10-90% non-condensing humidity rating. If you need to have a board used in a more harsh environment, ask to have humi-seal after final test.


    PCI-ECL Benefits

  • Speed
    		•  PCI-ECL is designed for speed. The PCI bus is supported with DMA and an internal holding FIFO. The State-Machines interoperate with the external data FIFO. The NECL IO can operate up to 250 MHz. A separate state machine keeps the data flowing between the internal and external FIFOs. True pipelined operation can be implemented between the system memory and the external device.


  • Price
    		•  PCI-ECL is reasonably priced to deliver the perfomance without bursting the budget. The extra features built into the PCI-ECL may save you card slots and dollars in your budget.


  • Ease of Use
    		•  PCI-ECL is easy to use. Windows® Drivers are available. Please download the manual and see for yourself. The engineering kit provides a good starting point for a new user.


  • Availability
    		•  PCI-ECL has been delivered to multiple customers and is being or has been integrated into their systems. As an in-stock item you will be able to send in your order and in most cases have your hardware the next day - delivered to you via FedEx. Please call the factory for current status


  • Size
    		•  PCI-ECL is a 1/2 size PCI board which conforms to the PCI mechanical and electrical specifications. Eliminate mechanical interference issues. Fits in the small form factor chassis as well as standard [full length].


  • PCI Compatibility
    		•  The PCI-ECL is universal voltage PCI compliant device. PCI-ECL can be expected to work in any PCI compliant backplane.


    Ordering Information and Manuals
    PCI-ECL.....................Standard board
    PCI-ECL-1..................Alternate vertical connector installed for internal wiring
    PCI-NECL-XG1
    Customer: XG Technology
    To include a Driver and/or Engineering kit w/order select


    Quantity


    Custom version for digital radio application. 170 MHz serial data in or out with Data, Clock and Enable signals. Two 16 bit NECL parallel Ports, 12 bit TTL IO. Please note that the default connector is the internal [-1] configuration.

    Download the PCI-NECL-XG1 Hardware revision A2 Manual 8/2/04 in PDF format.

    Download the PCI-NECL-XG1 XP/2000 Driver Manual 8/24/04 in PDF format.

    PCI-NECL-ASN1
    Customer: Asine Ltd.

    Custom Parallel interface. Programmable 16 bit parallel word rate with hardware handshaking. Transmit or receive. 12 bits uncommitted TTL IO.

    Download the PCI-NECL-ASN1 Hardware revision B Manual 2/5/04 in PDF format.

    Download the PCI-NECL-ASN1 XP/2000 Driver Manual 8/24/04 in PDF format.


    Engineering Kits

    Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. We recognize that different customers have different needs. The Engineering Kits are standardized in description to help with selection. The kits are segmented to allow for customers who only need hardware support, software support or a mixture. The Engineering Kit is highly recommended for first time buyers. The kit pricing is discounted to encourage their use.

    PCI-ECL-Eng-1 .......... Hardware Support Engineering Kit includes:
    Board level Schematics [PDF], HDEterm100, HDEcabl100, reference VHDL implementation

    PCI-ECL-Eng-2 .......... Hardware Support plus Driver Engineering Kit includes:
    Board level Schematics [PDF], Software[PCI-ECL Driver and sample application zip file ], HDEterm100, HDEcabl100.

    PCI-ECL Drivers.......... Software Support Only Windows®XP and 2000 compliant drivers for the PCI-ECL.
    Please see the Driver manual for the specifics of using the driver. Please note that the driver includes "generic" capabilities to allow you to use the driver with your custom modified VHDL or with our customerized versions..


    PLL Support



    Download the CyberClocks R2.01.00 software
    right click on the above link to download and save the cyberclocks zip folder to your target


    Related Products


    HDEterm100 100 position terminal block with D100 cable interface for PCI-ECL
    HDEcabl100 PCI-ECL compatible cable
    .

    HDEcabl100-ECL-crossover
    HDEcabl100-ECL-crossover The PCI-ECL cross-over cable has cross over connections for the "ECL out" and "ECL in" [19-0] differential pairs plus straight through connections for the TTL [11-0] and ground. The cable allows direct board to board connections with a common pinout on the board side. Download the PCI-ECL crossover cable pinout in PDF format.
    Straight through cables are also available (HDEcabl100). Both are compatible with the PCI-ECL and HDEterm100.


    Custom, IP, PMC, cPCI, PCI, PC*MIP, VME Hardware, Software designed to your requirements

    Try before you buy program


    Home | IndustryPack | PMC | PCI | cPCI | PC/104p | Engineering Services | News
    Search the Dynamic Engineering Site