PCIeBiSerialDb37
PCIe Compatible Bi-Directional Serial Data Interface

PCIeBiSerialDb37-LM9 shown.


The BiSerial family has been expanded again to add PCIe; featuring a Spartan III [Xilinx] FPGA, 1-4 lanes of PCIe operation, RS-485/RS-422 and or LVDS IO. Building on the knowledge and experience gathered from multiple PC104p, IP and PMC BiSerial implementations and adding in the latest technology has created the PCIeBiSerialDb37 The DB37 connector provides a different set of IO cabling options. The PMC BiSerial III can be used along with the PCIeBPMCX1 if you need a SCSI connector or more IO. The BiSerial features completely isolated FIFO´s with 32 bit ports for increased adaptability and performance. The [18] RS-485 / LVDS buffers have programmable termination, and direction control. Half-Duplex, Full-Duplex and single ended systems can be configured with software and VHDL. The denser, faster FPGA will implement the most complex state-machines. Please note that the design similarities will allow other BiSerial projects to be ported to the new member efficiently.

PCIeBiSerialDb37 is recommended for new designs. The initial version has an ARC-210 interface plus GPIO port. Supported with Windows® and Linux drivers. Please refer to the PMC BiSerial III Dynamic Data Sheet for more projects on a similar platform. Other designs to date have used custom serial protocols, manchester encoding and decoding, and SDLC with custom options for parity, CRC and more. The hardware has been used to interface with a wide variety of equipment. What do you need to communicate with? Control? Capture data from? Please see the bottom of this page for descriptions and manuals for our customerized versions.

Two external [to the FPGA] FIFO´s are available with 512K bytes each. The FIFO´s are 32 bits wide to optimize data transfer from the PCI bus. The interface is optimized to minimize the latency on the PCI bus. The data transfer size can be any length on the IO side. The FIFO´s support internal loop-back testing. The loop-back test can be used for BIT and for software development. The programmable FIFO flags are supported on both sets of FIFO´s. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any depth to allow the software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size. The interrupts are programmable and provisions are made to allow polling.

With the Spartan III 2000 and 4000 up to 48K x 32 of FIFO can be configured making for multiple channels with internal memory support. In addition the internal memories can be configured as Dual Port RAM to allow direct addressing and re-transmission of repeated patterns.

PCIeBiSerialDb37 has 18 transceivers which can be used for any combination of input and output functions. Parallel and serial data, multiple channels, and different hand-shaking schemes can be implemented with the quantity of IO on the BiSerial. The RS-485 transceivers support up to 40 MHz. clock and data rates. The LVDS transceivers are rated at better than 200 MHz.

The base design has a clock multiplexer coupled with a programmable divider to provide PCI, local oscillator, PLL [ 4 clocks available], and external clocking options along with divided versions. Custom oscillator frequencies can be installed when an exact frequency is required. The standard oscillator is 50 MHz. The DCM in the FPGA along with the PLL can be used to create custom frequencies based on readily available references to allow quick turn prototyping, and on-the-fly frequency changes.

"Channelized DMA"™ is an important feature of the BiSerial design. With "Channelized DMA"™ you have a separate DMA engine for each channel within the BiSerial design. Each state-machine can be serviced independently with DMA without requiring intervention from the host. Large data transfers can happen between multiple connections while the CPU is off doing something else. In non-channelized designs the CPU will have to intervene each time a different port needs to be serviced. With a channelized approach the hardware takes care of the local arbitration, and eliminates the intervention for better system performance and less latency. With a non-channelized approach the local FIFO size becomes the limiting factor as the CPU will have to service each channel before the local FIFO is over/under-run. The channelized approach effectively eliminates this bottleneck since the HW takes care of the "service."

If your situation demands a custom application; we will update the FPGA to meet your requirements. Send us your timing; we will send you the interface.
Please refer to the bottom of this page for previously completed "customerized" PCIeBiSerialDb37 implementations.
email us your wish list or call today

PCIeBiSerialDb37 Example Block Diagram

PCIeBiSerialDB37 LM9 version block diagram
See the bottom of Dynamic Data Sheet for more options


PCIeBiSerialDb37 Features

Size	Standard 1/2 length PCIe card
IO Speeds	Up to 40 MHz RS485, and up to 200 MHz LVDS signaling supported. Clock generator and PLL. PLL has 4 programmable outputs connected to the FPGA. 50 MHz reference for PLL with alternate frequencies available.
PCI Speed	Standard 33 MHz. operation over the Industrial temperature range. 50 MHz for commercial temperature designs. "Channelized DMA"™.
PCIe Speed	1-4 lane operation.
PCI Access Width	Standard 32 bit operation supported.
Software Interface	Registers are read-writeable. Transmit and Receive functions separated. Base functions separated. Flat or heirarchical applications supported. Windows® and Linux drivers support heirarchical access. With each interface independent each interface is less complex to control.
Interrupts	Transmit and Receive state-machine, FIFO Programmable almost empty [transmit] and programmable almost full [receive] . Programmable interrupts on error conditions [overflow, underflow, parity, etc.]. DMA is supported with interrupts. All interrupts are maskable and status can be polled for non-interrupt driven operation.
Signaling	18 RS-485 / RS-422 / LVDS compatible IO are provided. Any combination of transmit or receive channels can be created. LVDS and RS-485 can be mixed. RS-485 bandwidth is lower when mixed [16 MHz]. Programmable termination. Pull-up and Pull-down option on IO to allow controlled level when tri-stated. Option for high or low state. 3.3V RS-485 can be used for lower power consumption.
IO	The IO is available via the bezel connector - DB37. The differential IO is properly routed with impedance control, pitch, and space plus matched lengths across all of the pairs. The length matching is from FPGA ball to DB37 cable contact.
Interface	Custom programmed interfaces are available. Please send us a timing diagram, and we can program one for you. Most interfaces can be adapted from our large library of designs within 1-2 weeks including the updated VHDL, Windows and or Linux Driver, reference manuals etc. We can support on-site [ours] integration to help you get your application level software working. Build on our experience to save you schedule and money. You can also choose one of the already completed versions and purchase that off-the-shelf.
Power	+12 and 3.3V from PCIe connector. Local 5V, 2.5V and 1.2V converted with on-board power supplies. No power cables are required for this design.
Memory	Separate FIFOs / Dual Port RAM are provided for all channels. Internal FPGA Block RAM memory modules for fast access. Optional discrete FIFO´s [128K x 32] are available.
FPGA	Xilinx Spartan III 2000 and 4000 models are installed based on client requirements.

PCIeBiSerialDb37 Benefits

Speed	The PCIeBiSerialDb37 is optimized for serial interfacing requirements. The FIFO memories and programmable interrupts off-load the CPU from most of the management other implementations require. The FIFO access is optimized for the PCI bus further reducing overhead by speeding up the data transfer. On the IO side the BiSerial has independent channel functions. Channels can operate at maximum rate in parallel. With the Spartan III "Channelized DMA"™ can be implemented and still have plenty of gates left for your application.
Price	The BiSerial is easily programmed to implement new functions. Many previously implemented "custom designs" are available too. Without the costs of schematic level design, layout, debugging etc. a modified BiSerial will represent a large cost savings in your budget.
Ease of Use	PCIeBiSerialDb37 is easy to use. Point and shoot - just fill the FIFO and set the start bit to get your custom protocol transmitting. Built in loop-back capabilities and engineering kits help with integration into your system. We can write a custom Windows® or Linux driver for you.
Availability	Dynamic Engineering works to keep the PCIeBiSerialDb37 in stock. Send in your order and in most cases have your hardware the next day. With a custom design a 1-2 week design period is usually required. We can support immediately with the another version then send updated FLASH Files later to help get your project going - right away. Please note that there may be some delay for designs using client defined mixed IO etc.
Size	PCIeBiSerialDb37 is a standard1/2 length PCIe card and meets the PCIe mechanical specifications. The PCIeBiSerialDb37 can be used in all PCIe slots with 4 or more lanes. We can cut-down the PCIe connector for 1 lane implementations. The edge of the PCIeBiSerialDb37 is clear to allow for horizontal mount industrial chassis applications.
PCIe Compatibility	PCIeBiSerialDb37 is PCIe compliant per the PCI-SIG specification.
PCI Compatibility	PCIeBiSerialDb37 is PCI compliant. PCIeBiSerialDb37 uses a Tundra PCIe 4 lane bridge to PCI for the PCIe connection and PCI interface contained within the FPGA.

Engineering Kits
PCIeBiSerialDb37-ENG-1
Engineering Kit for PCIeBiSerialDb37 includes: Board level Schematics [PDF], Reference Software [WIN XP/2000 Driver Visual C ZIP file or Linux TAR file], Loop-back plug.

Customer Special Versions & Manuals
You can order these too or request that we design one for you

PCIeBiSerialDb37 version LM9
Customer: Lockheed Martin
The LM9 protocol implemented provides an ARC-210 compatible interface plus a GPIO port. The main purpose is to allow data communications using the ARC-210. The ARC-210 interface is bidirectional and is fully independent for Tx and Rx. Each side is supported with 4Kx32 Data FIFO plus 2Kx32 Packet FIFO. The transmitter "SendTiming" signal can be set to output the reference clock to allow for loop-back and alternate purpose uses. Interrupt or polled operation. "Channelized DMA"™ on TX and RX. 12 bit GPIO port [termination, direction independent on each bit]. RS-485 IO. TX in transmit SendTiming mode supported with PLL for user frequency.

LM9 simplified transmit timing diagram

Download the LM9 Hardware manual
Download the LM9 Windows® manual
Download the LM9 Linux manual



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