150 DuBois St. Suite #3
Santa Cruz, Calif. 95060
(831) 457 8891 (831) 457 4793 Fax
Est. 1988


PMC-Parallel-485



A simple point and shoot interface makes it easy to add up to 34 differential IO to your system with the PMC Parallel 485. The PMC compatible PMC-Parallel-485 design adds 32 [RS-485 /RS-422/LVDS] differential IO lines to one slot of your carrier board. 2 additional differential pairs are available for a clock & clock enable. The signals can be used to capture data with an external reference or programmed to be references for the rest of the system. Many standard features and ease of VHDL updating make PMC Parallel 485 a versatile design.

Each channel is software programmable to be an input or an output. The lower four bits are independent. The rest are programmed on a nibble basis.

Each channel is software programmable to be terminated or not. The lower four bits are independent. The rest of the bits are programmed on a nibble [4 bit group] basis.

A high density 68 pin SCSI III front panel connector and backplane IO provide system wiring options.

The IO channels can be used as interrupt generators. Interrupts are programmable to be based on level or edge and active high or low. The registers are mapped as 32 bit words and support byte, word and 32 bit access. All registers are read-writeable.

An 8 bit user switch is provided to allow custom configurations to be easily and automatically configured with a common software driver. For example; the switch can be read through the status port and used to determine what the RX/TX configuration should be and any special characteristics for that implementation.

All of the data bits pass through the FPGA used to implement the PCI interface. Any or all bits can be used for custom state machine and IO functions. Custom termination options are also available. Please contact Dynamic Engineering with your requirements.


  • Size
    		•  Single wide PMC.

  • Parallel Interface
    		•  32 independent differential channels. Each channel can be an input or an output.
  • Clocks
    		•  2 additional differential pairs for clock and clock enable.
    Software selectable direction control. Could be programmed for other purposes [FPGA].
  • State Machine
    		•  All bits are fed back through the FPGA to allow custom interfacing options.
    Contact the factory for implementation.

  • Interface
    		•  RS-485 compatible transceivers. Also compatible with RS-422 requirements.

  • Termination Resistor
    		•  Selectable switch plus resistor equivalent resistance.
    Selectable direction control.
  • User Bits
    		•  8 switch positions are mapped through the Status Register
    to allow user configuration information to be read with software.

  • Software Interface
    		•  32 bit registers.
    Read-back of channel control registers and input
    registers. Read-write of control register for card configuration.

  • Interrupts
    		•  All IO Channels can be programmed to cause interrupts. Each
    channel is programmable to be masked, active hi, active low, edge
    triggered. Interrupts are mapped to INTA on PCI bus.

  • Power Requirement
    		•  300 mA at +5V typ.


  • External Clock
    		•  Input registers are programmable to capture data on the internal
    clock, user oscillator or external user supplied clock. Additionally an
    external clock enable input is provided to allow selective clocks to
    be gated at the register. SW can select internal or external
    source for clock and clock enable.

  • Internal Clock
    		•  The Input registers can be clocked with an internally generated
    clock derived from the PCI reference. The rate is programmable
    with 8.25 MHz., 4.125 MHz, 2.063 Mhz., 1.031 Mhz.,
    515.6 Khz. selectable based on a 33 Mhz. PCI clock.
    User frequency oscillator position is also available. Oscillator clock rate can be used directly or divided down. All clock options programmable under software control.


    Custom Versions
    -NG1..........PMC-Parallel-485NG1
    Modified version with programmable counter timers, alternate interrupt implementation, clock generators and more. Please download the manual for details.

    -NRC1..........PMC-Parallel-485-NRC1
    Modified version with interrupt on change of state capability, upper bits muxed to allow input buffering or discrete outputs, and upper nibble predefined as output. Engineering kit available. Please download the manual for details.


    Engineering Kits

    PMC-Parallel-485-ENG-1..........Engineering Kit for PMC-Parallel-485 includes:
    Board level Schematics [PDF], Reference Software [WIN NT, WinRT, Visual C ZIP file], 3' HDEcabl68 and HDEterm68.
    PMC-Parallel-485-ENG-2 ..........Engineering Kit includes:
    PCI2PMC adapter card, board level Schematics [PDF], Reference Software [WIN NT, WinRT, Visual C ZIP file], 3' HDEcabl68 and HDEterm68-M.


    Download the PMC-Parallel-485 Manual updated 4/30/03 in Adobe Acrobat PDF format.
    Download the PMC-Parallel-485 NG1 version Manual updated 9/17/00 in Adobe Acrobat PDF format.
    Download the PMC-Parallel-485 NRC1 version Manual updated 4/30/03 in Adobe Acrobat PDF format.
    Related: HDEcabl68 SCSI II/III Cable HDEterm68 SCSI II/III to 68 pin terminal block


    Custom, IP, PMC, PC*MIP, PCI, VME Hardware, Software designed to your requirements
    Try before you buy program

    Dynamic Engineering's Hardware and Software design overview
    Home | IndustryPack | PMC | PCI | Engineering Services | News | Search the Dynamic Engineering Site