| Size |
Single wide PMC. |
| |
|
| Parallel Interface |
32 independent differential channels. Each channel can be an input or an
|
| |
output.
|
| Clocks |
2 additional differential pairs for clock and clock enable.
|
|
Software selectable direction control. Could be programmed for other purposes [FPGA].
|
| State Machine |
All bits are fed back through the FPGA to allow custom interfacing options.
|
|
Contact the factory for implementation.
|
| |
|
| Counter Timers |
Programmable
|
| |
|
| Interface |
RS-485 compatible transceivers. Also compatible with RS-422 requirements.
|
| |
|
| Termination Resistor |
Selectable 180 ohm equivalent resistance.
|
|
Selectable direction control.
|
| User Bits |
8 switch positions are mapped through the Status Register
|
|
to allow user configuration information to be read with software.
|
| |
|
| Software Interface |
32 bit registers. Read-back of channel control registers and input registers. Read-write of control register for card configuration.
|
| |
|
| Interrupts |
All IO Channels can be programmed to cause interrupts. Each channel is programmable to be masked, active hi, active low, edge triggered. Interrupts are mapped to INTA on PCI bus.
|
| |
|
| Power Requirement |
300 mA at +5V typ.
|
| |
|
| |
|
| External Clock |
Input registers are programmable to capture data on the internal clock, user oscillator or external user supplied clock. Additionally an external clock enable input is provided to allow selective clocks to be gated at the register. SW can select internal or external source for clock and clock enable.
|
| |
|
| Internal Clock |
The Input registers can be clocked with an internally generated clock derived from the PCI reference. The rate is programmable with 8.25 MHz., 4.125 MHz, 2.063 MHz., 1.031 MHz., 515.6 KHz. selectable based on a 33 MHz. PCI clock.
|
| |
|
| | User frequency oscillator position is also available. Oscillator clock rate can be used directly or divided down. All clock options programmable under software control.
|
| |
|