PMC_XM - The PMC-XM is intended for use in situations where the user wants to control the design. PMC-XM has two FPGA devices built in. The first device takes care of the PCI interface, DMA etc. [Spartan III] The second device [Virtex XC4VSX35-10] is for the user application. The Transition Module [XM] is attached to the Virtex device. The Virtex is further supported by a 1M x 36 QDR SRAM, PLL, Digital Temperature Sensor, and connections to the PMC Pn4 connector. Four LEDs are supplied to the Virtex to provide design status, debugging support and other user purposes. The user mezzanine is designed with exposed metal on the perimeter to allow a "can" to be used with the mezzanine for RF applications. Other user mezzanine designs are possible. The Virtex has a built in CPU which coupled with the QDR provides a great DSP engine for recursive processing. The Virtex has plenty of gates for pipelined processing. The design has been expanded to include the "DIFF" and "TTL" versions which have built in IO to remove the need for the transition module for more generalized design requirements.
DF Set - Hardware performs the A/D, Auto and Cross correlation functions, and provided the results to a general purpose CPU for data reduction, and LOB calculation. A four card implementation which features real time parallel processing to maximize system performance. This design was later converted to gate arrays allowing a single card implementation.
AMM - Nubus card design which performs the compression and decompression of video data. The data is read into the card using block mode transfers over the Nubus in RGB format, is converted to YUV rotated in 32 bit format, and compressed with a proprietary repeated code compression technique. The compressed data is stored within a 32 Mb DRAM array on board. The board also performs the playback function. High speed paths, FIFO coupling, and 4 Xilinx 4000 series parts make this a high performance design.
PCI_LVDS_8R - PCI based LVDS receiver interface with 8 channels based on National DS90CR218. Each channel is received and filtered by a Xilinx device then stored into a FIFO. The FIFO is read and the data stored into SDRAM. Once captured the data is written to host memory via scatter-gather DMA. The channels are programmable for filtering and are fully independent for clocking.
PCI_LVDS_8T - PCI based LVDS transmitter interface with 8 channels based on National DS90CR217. Data is read into the card with DMA and stored into the local SDRAM. Each channel can be assigned a different area of memory to operate from. The data is read out with the option of a snap-shot or repeated data. The data can be repeated in a single loop or with a dual loop - inner and outer. The data can be further expanded with a programmable count and 4 trigger patterns. The channels can be interlocked to provide a coherent start. External triggers allow for intra-board synchronization of channels.
