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Time Of Day Interface

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IP-HaveQuick Description

  • Manchester Encoder and Decoder - Master and Target operation
  • 1 PPS supported
  • TOD : Hours, Minutes, Seconds, Day of Year, Year, TFOM
  • FPGA controlled allowing for customized models
  • Industrial Temperature components standard
  • 1 year warranty standard. Extended warranty available.
  • ROHS and Standard processing available
IP-HaveQuick is part of the IndustryPack® Module family of modular I/O components by Dynamic Engineering. IP-HaveQuick is built on the IP-Parallel-HV PCB. IP-Parallel-HV provides high voltage interfaces with programmable state-machines. 24 Inputs and 24 outputs make serial and parallel interfaces possible. The HaveQuick protocol provides both target and master operation with software selection. The data is Manchester encoded BCD with a modified Hamming code that uses four data bits and four check bits for each decimal digit of the time code. Time Figure of Merit included.

IP-HaveQuick Timing Diagram

The target will wait for the 1 PPS signal then synchronize with the manchester encoded data. The data carries the time code. Once synchronized, and the data validated, the decoded data is stored for reading by the host computer. Programmable interrupts can be used to alert the system when new time code is available. The time code provides very accurate time - to the second. The hardware interpolates and provides higher resolution time which is re-synchronized with each 1PPS pulse received.

IP-HaveQuick Block Diagram

In Master mode the 1PPS signal, data and discrete are output from IP-HaveQuick. The data in master mode comes from a counter with has presettable fields. Software can preset the year, day, hour, minute, second, and quality factor. Software will start operation by setting the transmit bit. The counter will increment and output the 1PPS once per second followed by the manchester encoded time code. The counter has a resolution of 1 microsecond allowing the local host better resolution to the current time. The outputs can be masked to support using IP-HaveQuick as a local high resolution timerr. Target mode is available when programmed in this manner.

The modes [Master and Target] are independent to allow both to be active for loop-back testing.

PCI implementations can be done with the PCI3IP and PCI5IP. Applications from 1-5 HaveQuick intefaces per PCI slot.
PCIe implementations can be done with the PCIe3IP and PCIe5IP. Applications from 1-5 HaveQuick intefaces per PCIe slot.
cPCI 3U is supported with the cPCI2IP. Applications from 1-2 HaveQuick intefaces per 3U cPCI slot.
cPCI 6U is supported with the cPCI4IP. Applications from 1-4 HaveQuick intefaces per 6U cPCI slot.
PC104p is supported with the PC104pIP. Add 1 IP-HaveQuick to your stack with this adapter.
PC104p situations with a custom mechanical can be done with the PC104p4IP. Up to 4 IP-HaveQuick using this adapter

IP-HaveQuick Features

1.8 x 3.9 inches nominal single slot IP Module. Type II with low profile devices on rear
IP Module IO connector
Compatible with 8 and 32 MHz IP bus operation. Oscillator position available
IP Decoding
ID, IO, Mem and INT spaces supported.
1PPS and HQ Data supported - Receive and Transmit. Programmable starting values when acting as Master.
Supports programmable synchronization pattern.
All IO are protected with current limiting resistors.
Interrupts can be used or polled mode operation.
Power Requirement
+5V, +12V.
SW Interface
All FPGA registers are read-write. All registers on word addresses.
Current Fab Number
Belcore 25c GB 1.855 Million Hours
There is room in the FPGA for custom applications. Send in your specifications and we can quote a custom version for you

IP-HaveQuick Benefits

The IP interface supports 32 MHz operation for quick data loading and unloading. The interface supports interrupts and polling. Dynamic Engineering carriers support 64 bit[PCIe models]/32 bit[PCI models] to 16 bit conversion in HW allowing for higher throughput and lower overhead. HaveQuick registers are LW aligned to support the higher throughput reads.
System level cost is best when reasonably priced reliable hardware is used and NRE minimized. With IP-HaveQuick, driver support for the carrier and IP level, reference software, history of reliable operation, and fantastic client support your cost per unit and overall costs are attractive. IP-HaveQuick is inexpensive and can save money in other ways too.
Ease of Use
IP-HaveQuick is easy to use. For Target operation just initialize and wait for the interrupt. Once synchronized with the system the interpolated data is available. As a master initialize to the current date and time then start. Please download the manuals and see for yourself. The User Application software and driver will get you up and running quickly. SIngle and multiple card capable. The example software includes loop-back testing. Interrupts are supported with the driver, and tested with the reference software.
The IP-Parallel-HV [IP-HaveQuick] family are stocked items.
IP Specification Compatibility
IP-Parallel-HV [IP-HaveQuick] is compliant per the VITA 4 - 1995 specification. Tested with PCI and PCIe based carriers. All Dynamic Engineering IP Modules are compatible with the PCIe3IP, PCIe5IP, VPXI2IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP etc. IP-Parallel-HV will operate with any IP specification compliant carrier board.

Part Number: IP-HaveQuick
Ordering Options

  • IP-HaveQuick Time Of Day receiver/transmitter using HaveQuick format data - manchester encoded with seconds, minutes, hours, days, year.

  • Other IP-Parallel-HV based designss
  • IP-Parallel-HV Standard Model with open collector register based IO. Programmable interrupts, user settable open collector reference.
  • -IP Crypto to interface with KYK-13 and similar interface. Read the key, provide to the host and remove data with approved method.
  • -Miller Add Miller encoded inputs and outputs to your system. See manuals tab for more information.
  • -Test Use IP-HV-TEST to develop a driver or test an IP Carrier. The Module responds to all 4 access types, allows testing of both interrupts, has 2K bytes of RAM and more to support your SW or HW development. See manuals tab for more information.

  • Add additional options to the "- number"
  • -ROHS Use ROHS processing. Standard processing is "leaded"
  • -CC Option to add Conformal Coating

IP-HaveQuick Drivers

Software Support for IP-HaveQuick includes: Windows® 10 compliant driver. Linux and VxWorks by request.
The IP driver is layered and operates on top of the Carrier driver. IP drivers are auto installed for each instance detected. Please see the Driver manuals for the specifics of each type.

Drivers and Reference SW are developed for each type / version of IP-Parallel-HV implemented. When custom versions are ordered the NRE will include providing Windows, Linux, and or VxWorks packages. For off-the-shelf models, select on the manuals tab, the Windows® and Linux SW shown is included with your purchase of the HW. A small one-time charge is required for the VxWorks versions. Unsupported SW versions may have an NRE requirement.

Integration support is available. Please contact Dynamic Engineering for this option or download the Technical Support Description from the Company button.

linux diagram
Reference diagam of how our Linux Driver / Application layer operate with the Carrier and IP Module.

IP-HaveQuick Manuals

Click on the links to Download selected manuals in PDF format.

IP Carrier and Module Quick Start guide for Windows®7
IP Carrier and Module Quick Start guide for Windows®10

IP-HaveQuick HW Manual
IP-HaveQuick Win10 Manual
VxWorks IP Module Manual
IP Carrier Linux Manual
Linux IP Module Manual

Other IP-Parallel-HV based designss
IP-Parallel-HV HW Manual
IP-Parallel-HV-Miller Miller Interface version with 1RX and 1 TX port. Programmable interrupt options, 1Kx16 FIFO per port.
IP-HV-Test Win10 Manual in PDF format. Use IP-Parallel-HV-TEST to develop a driver or test an IP Carrier. The Module responds to all 4 access types, allows testing of both interrupts, has 2K bytes of RAM and more to support your SW or HW development.