25 years of PMC BiSerial models and counting. PMC-BiSerial-VI includes a Spartan 6 [Xilinx], DDR, PLL, Differential IO [LVDS or RS-485 or mixed], programmable terminations, DMA and build options for front or rear IO. PMC-BiSerial-VI incorporates industrial temperature or better components. The block RAM within the 100 size Spartan VI provides enough internal RAM for many designs. The DDR expands that memory for systems where large amounts of storage are required. Building on the knowledge and experience gathered from multiple IP and PMC BiSerial implementations and adding in the latest technology has created Revision 7 of PMC-BiSerial-VI. The latest updates include replacing the previous model external FIFOs with DDR for a massive upgrade in storage, upgrading the termination switches, and adding temperature measurement.
The 34 IO can be configured to support one function, one function replicated several times, or multiple functions. For example: "UART" has 8 UART channels, while the "ORB2" has 8 channels with 4 different functions. A real space saver when you need to have some Manchester to go with your UART and HDLC ports. A partial list of functions implemented in "Channels" includes:
Manchester, Miller, SDLC, HDLC, UART, Serial, Parallel, GPIO, COS, Custom, LADEE, NMS, Camera, Ternary, Low Speed, High Speed, Telemetry, Master & Target interactive IO, Adaptive. To support the functions the designs include: memory elements instantiated with FIFO, Dual Port RAM, register files, as well as state-machines, counters, timers, dividers, registers, CRC and Parity generation/checking, software drivers and applications, DMA [direct memory access] and the glue that goes with it. Our designs are all written in VHDL and done in a heirarchy allowing direct porting of different features to create new implementations.
More than 50 customerized versions of the BiSerial family and counting. IP-BiSerial-VI, PMC-BiSerial-VI, PC104p-BiSerial-VI, PCIe-BiSerialDb37, and PMC-BiSerial-6T20 are recommended for new designs.
The hardware has been used to interface with a wide variety of equipment. What do you need to communicate with? Control? Capture data from? Please see the tabs for current and previous portable BiSerial implementations. Descriptions and manuals available. We have been doing custom versions of the BiSerial since 1998 when the IP version was released.
A new custom version can be implemented in a very reasonable time. Typically 2-3 weeks of design time for a medium sized project including the new VHDL set, Windows® or Linux driver, reference software package, and documentation. Examples of the designs performed to date are listed . Please use the tabs to see the current and previous versions of BiSerial.
We can be rapid with our response because the designs are structured to allow channels to be moved in and out to create new design sets. Most designs have a fairly large component of reused "known good" VHDL that we can pull from allowing us to focus on the new functions required for your implementation. You are getting the benefit of many man-years of design and test time with each new version created.
Join our high reliability clients by taking advantage of our know-how to help speed your project to completion.
PMC-BiSerial-VI can be used along with a PCIe or other carrier/adapter to use with a variety of system types - PCI, PCIe, PC104p, VPX cPCI, etc. Dynamic Engineering has PMC carriers for PCI, PCIexpress, cPCI, PC104p, and can do custom designs specific to client requirements as well. Please use the handy JAVA pull-down menu at the top of any page to navigate to other Dynamic Engineering products including carriers.
PMCs are independently specificed through VITA for the form factor, connectors and pinouts of the PCI signaling; you can use PMC-BiSerial-VI with any carrier from any vendor that supports standard PMCs. PMC-BiSerial-VI features a 3.3V PCI interface..
It all starts with the PCB [Printed Circuit Board]. Quality design and quality materials are required to meet the strenuous requirements of many of our implementations. You can do the job quickly or you can do the design correctly. We pride ourselves on taking the time to put the extra work into our layouts. The quality goes in before the parts go on. In addition to routing strategy and layer counts, Via size, plating requirements, break-out trace widths, and materials are areas where quality comes into play. The via size and method of trace attachment to the via affect the signal shape and reliability. Using tear-drop trace connections to pads, vias and through hole components enhance the reliability and minimize the impedance discontinuity resulting in a cleaner signal. Calculating the size and quantity of vias to provide adequate copper for proper power distribution and thermal aspects. Working the stack-up to allow larger trace widths for a given impedance provides better vibration endurance. The design has several power planes with sufficient copper weight and coverage to provide the references required for the routing plus the current and voltages needed by the various devices on the board.
Since 1998 when the IP BiSerial was introduced, the BiSerial family has enjoyed an excellent track record for reliability.
The PCI interface has a published set of requirements for compliance which restrict length, impedance, loading and other factors. PMC-BiSerial-VI is compliant with the PCI Specification. The IO section has requirements based on the IO type and the purpose for the IO. A very conservative approach has been taken to allow operation with any client requirement. The IO can be LVDS or RS-485. The IO on the connector side is differential with a 100 ohm impedance requirement. Between the FPGA and the tranceivers the IO is single ended. Each IO has separate direction, termination, and data lines to allow complete flexibilty. The design has matched length connections from the FPGA ball to the seating plane of the connector. The lengths are matched to the "mil". The Impedance is controlled and the signals routed with proper spacing to avoid cross talk etc. The other features including memory, PLL, oscillator, and power supplies are implemented within the PCB to exceed the operational requirements for those devices.
The FPGA has internal block RAM which can be configured in a variety of ways. Currently, up to 268 BRAMs can be configured for internal memory support. In addition, the memory can be configured as Dual Port RAM to allow direct addressing and retransmission of repeated patterns.
Sometimes you just need more memory. New with Revision 7 is DDR with 256 Mbytes. The DDR is supported with FPGA based FIFOs and a controller to allow more than one port to use the memory. Internal loop-back is supported. The loop-back test can be used for BIT and for software development. Programmable FIFO flags are supported on both sets of FIFOs. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any depth to allow the software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size. The interrupts are programmable and provisions are made to allow polling. DMA can be programmed to fill or empty the FIFO with sizes larger than the FIFO size. DMA is hardware controlled to be held off when no data is available or no room is available. Software can set the amount allocated to each function supported by the DDR. With the "Channelized DMA"™ capability and large FIFOs the software application can have reduced interrupt counts to deal with while supporting larger and faster IO transfer rates.
PMC-BiSerial-VI has 34 transceivers which can be used for any combination of input and output functions. Parallel and serial data, multiple channels, and different hand-shaking schemes can be implemented with the quantity of IO on the PMC-BiSerial-VI. RS-485 transceivers support up to 50 Mbps rates. The LVDS transceivers are rated at better than 200 MHz.
The IO is available through either the front panel mounted SCSI III connector or Pn4 or some combination. Each transceiver pair is isolated from the connector with zero ohm resistors. The resistors are mounted front and rear and tied together at each pin to allow for a stub length of 1/16th in. The Connectors are routed from the resistors directly allowing for almost zero stub lengths and the option to connect front or rear IO options. Two banks of transorbs are used to provide signal protection near each of the connectors. Installed bank matched to connector selected.
Clock options are frequently a major factor in embedded designs. Getting the right reference to the right part of the design and allowing for local control of exact frequencies. PMC-BiSerial-VI has a PLL with 4 programmable outputs, reference oscillator, internal DCMs and buffering plus programable dividers instantiated within the VHDL. The PLL can be programmed to "any" fixed frequency, the DCM used to create phase variations, and local dividers to allow on-the-fly channel based frequency changes.
"Channelized DMA"™ is an important feature of the PMC-BiSerial-VI design. With "Channelized DMA"™ you have a separate DMA engine for each transmitter and each receiver within each channel. Each state-machine can be serviced independently with DMA without requiring intervention from the host. Large data transfers can happen between multiple connections while the CPU is off doing something else. In non-channelized designs the CPU will have to intervene each time a different port needs to be serviced. With a channelized approach the hardware takes care of the local arbitration, and eliminates the intervention for better system performance and less latency.
If your situation demands a custom application we will update the Xilinx FPGA and IO components. Send us your timing and we will send you the interface. Please refer to the previously completed "customerized" PMC-BiSerial-VI implementations.
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PMC-BiSerial VI Example Block Diagram

PMC BiSerial III ORB2 version block diagram
PMC Modules require a "carrier" in most cases to adapt them to the system. Dynamic Engineering has carrier solutions for a variety of formats.
PCIe implementations can be done with the
PCIeBPMCX1 and
PCIeBPMCX2.
PCI implementations can be done with the
PCI2PMC and
PCIBPMCX2.
cPCI 3U is supported with the
cPCIBPMC3U32
cPCI 6U is supported with the
cPCIBPMC6U.
PCI-104 is supported with the
PCI104p2PMC.