PC104p-BiSerial-VI

The BiSerial family has been updated to include PC104p-BiSerial-VI, a Spartan 6 [Xilinx] based card with expanded capabilities. BiSerial VI includes industrial temperature components, and more internal RAM, clocks and gates for more complex designs. Building on the knowledge and experience gathered from multiple IP, PMC, and PC104p BiSerial implementations and adding in the latest technology has created PC104p-BiSerial-VI. BiSerial VI features completely isolated FIFO´s with 32 bit ports for increased adaptability and performance. The FIFO´s can be configured to support RX or TX or both directions. The [16] RS-485 / LVDS buffers have individual programmable termination, and direction controls allowing for any combination of "In´s and Out´s". Half-Duplex, Full-Duplex and uni-directional systems can be configured with software and VHDL. The denser, faster FPGA will implement the most complex state-machines. In addition the 8 single ended plus analog IO can save space in your system.

The 16 differential IO can be configured to support one function, one function replicated several times, or multiple functions. For example the "BA14" has 1 port with a selector to choose from 1 of 8 inputs plus broadcasts on 8 outputs. Many designs on the PMC, IP, and previous PC104p designs can be ported to PC104p-BiSerial-VI. A partial list of functions implemented in "Channels" includes: Manchester, Miller, SDLC, UART, Serial, Parallel, GPIO, COS, Custom, LADEE, NMS, Camera, Ternary, Low Speed, High Speed, Telemetry, Master & Target interactive IO, Adaptive. To support the functions the designs include: memory elements instantiated with FIFO, Dual Port RAM, register files, as well as state-machines, counters, timers, dividers, registers, CRC and Parity generation/checking, software drivers and applications, DMA [direct memory access] and the glue that goes with it. Our designs are mostly written in VHDL [small amount of verilog] and done in a heirarchy allowing direct porting of different features to create new implementations.

The hardware family has been used to interface with a wide variety of equipment. What do you need to communicate with? Control? Capture data from? Please see the bottom of this page and other BiSerial implementations for descriptions and manuals for our customerized versions. We have been doing custom versions of the BiSerial since 1998 when the IP version first came out. We will continue custom versions in the future with the next generation parts and features.

A new custom version can be implemented in a very reasonable time. Typically a few weeks of design time for a medium sized project including the new VHDL set, Windows® or Linux or VxWorks driver, reference software package, and documentation.

We can be rapid with our response because the designs are structured to allow channels to be moved in and out to create new design sets. Most designs have a fairly large component of reused "known good" VHDL that we can pull from allowing us to focus on the new functions required for your implementation. You are getting the benefit of many man-years of design and test time with each new version created. Join our high reliability clients by taking advantage of our know-how to help speed your project to completion.

PC104p-BiSerial-VI can be used along with a stack, PCIe or other carrier/adapter to use with a variety of system types - PCI, PCIe, PC104p, etc. Dynamic Engineering has PCI-104 carriers for PCI, PCIexpress, and supports other elements of PC104 stacks with power supplies, cooling, chassis, dedicated IO types [SpaceWire etc.],

PC104p Devices´s are independently specificed through teh PC104 consortium for the form factor, connectors and pinouts of the PCI signaling; you can use the PC104p-BiSerial-VI design with any device from any vendor that supports standard PC104p´s. To make it even easier the PC104p-BiSerial-VI has a universal PCI design to allow operation with VIO set to 3.3 or 5V.

It all starts with the PCB [Printed Circuit Board]. Quality design and quality materials are required to meet the strenuous requirements of many of our implementations. You can do the job quickly or you can do the design correctly. We pride ourselves on taking the time to put the extra work into our layouts. The quality goes in before the parts go on. In addition to routing strategy and layer counts, Via size, plating requirements, break-out trace widths, and materials are areas where quality comes into play. The via size and method of trace attachment to the via affect the signal shape and reliability. Using tear-drop trace connections to pads, via´s and through hole components enhance the reliability and minimize the impedance discontinuity resulting in a cleaner signal. Using 8/10/12 mil vias provides adequate copper for proper power distribution and more surface area to bond to where traces are interconnected. The combination provides better vibration endurance than smaller vias and traces would provide. The design has several power planes with sufficient copper weight and coverage to provide the references required for the routing plus the current and voltages needed by the various devices on the board. The larger features make the design work more difficult since there is less room to "play with" and the end result is worth it. Since 1998 when the IP BiSerial was introduced, the BiSerial family has enjoyed an excellent track record for reliability.

The PCI interface has a published set of requirements for compliance which restrict length, impedance, loading and other factors. PC104p-BiSerial-VI is compliant with the PCI Specification. The IO section has requirements based on the IO type and the purpose for the IO. A very conservative approach has been taken to allow operation with any client requirement. The differential IO can be LVDS or RS-485. The IO on the connector side is differential with a 100 ohm impedance requirement. Between the FPGA and the tranceivers the IO is single ended. Each IO has separate direction, termination, and data lines to allow complete flexibilty. The design has matched length connections from the FPGA ball to the seating plane of the connector. The lengths are matched to the "mil". The Impedance is controlled and the signals routed with proper spacing to avoid cross talk etc. The TTL IO is separately matched and the analog section is isolated from the other signaling. The other features including memory, PLL, oscillator, and power supplies are implemented within the PCB to exceed the operational requirements for those devices.

The Spartan VI has internal block RAM which can be configured in a variety of ways. Currently, up to 268 BRAMs can be configured for internal channel memory support. In addition the memory can be configured as Dual Port RAM to allow direct addressing and retransmission of repeated patterns.

Sometimes you just need more memory. Two external [to the FPGA] FIFO´s are available with 128Kx32 each. The FIFO´s are 32 bits wide to optimize data transfer from the PCI bus. Internal loop-back is supported. The loop-back test can be used for BIT and for software development. Programmable FIFO flags are supported on both sets of FIFO´s. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any depth to allow the software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size. The interrupts are programmable and provisions are made to allow polling. In addition DMA can be programmed to fill or empty the FIFO with sizes larger than the FIFO size. The DMA is hardware controlled to be held off when no data is available or no room is available. With the "Channelized DMA"™ capability and large FIFO´s the software application can have reduced interrupt counts while supporting larger and faster IO transfer rates.

PC104p-BiSerial-VI has 16 transceivers which can be used for any combination of input and output functions. Parallel and serial data, multiple channels, and different hand-shaking schemes can be implemented with the quantity of IO on the PMC-BiSerial. RS-485 transceivers support up to 50 MHz. rates. The LVDS transceivers are rated at better than 200 MHz.

The IO is available through a right angle 2x25 shrouded header. Each transceiver pair is isolated from the connector with zero ohm resistors. The Connector is routed from the resistors directly allowing for almost zero stub lengths and the option to connect front or rear IO options. In addition the IO have resistors tied between the IO and a power plane. The plane is strappable to allow 5V or GND on either rail. The IO can be set to provide a high or a low condition when not driven to support half duplex operation without adding resistors to your cables. For protection the IO are protected by TVS devices.

Clock options are frequently a major factor in embedded designs. Getting the right reference to the right part of the design and allowing for local control of exact frequencies. PC104p-BiSerial-VI has a PLL with 4 programmable clocks, reference oscillator, internal DCM´s and buffering plus programable dividers instantiated within the VHDL. The PLL can be programmed to "any" fixed frequency, the DCM used to create phase variations, and local dividers to allow on-the-fly channel based frequency changes.

"Channelized DMA"™ is an important feature of the PC104p-BiSerial-VI design. With "Channelized DMA"™ you have a separate DMA engine for each transmitter and each receiver within each port. Each state-machine can be serviced independently with DMA without requiring intervention from the host. Large data transfers can happen between multiple connections while the CPU is off doing something else. In non-channelized designs the CPU will have to intervene each time a different port needs to be serviced. With a channelized approach the hardware takes care of the local arbitration, and eliminates the intervention for better system performance and less latency.

If your situation demands a custom application we will update the Xilinx FPGA and IO components. Send us your timing and we will send you the interface. Please refer to the bottom of this page for previously completed "customerized" PC104p-BiSerial-VI implementations.
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PC104p-BiSerial-VI Example Block Diagram

PC104p Modules can be used with a "carrier" to adapt them to non-PC104p stack environments or used within a stack. Dynamic Engineering has carrier solutions for a variety of formats.
PCI implementations can be done with PCI2PC104p for single cards - passive adaptation.
PCI implementations can be done with PCIBPC104pET for single or stacks - bridged model.