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Maxwell-2
Develop your next project using Maxwell-2. FPGA, Memory, IO, power supplies all built in. Use local CPU [MicroBlaze in FPGA] or control over the IO.
Maxwell-2 Description
- Spartan-VI LX45-3 standard
- QSPI FLASH
- DDR 128Mx16
- Parallel Ports, Buffered 20 IO Out, In
- Parallel Port 20 bit bidirectional
- Temperature Sensor
- FRAM 8Kx8
- USB - mini B
- Ethernet - RJ45 with LEDs 10/100
- RTC - Real Time Clock with battery back-up
- Multiple Clock references for FPGA- 100 MHz, 50 MHz, 25 MHz, 32 KHz, 1 Hz,
- 13 User LEDs
- Switches: Power Slide, User Dip (8), 2 User push button [momentary]
- JTAG programming, flying lead and ribbon cable header connectors
- Industrial Temperature components
- 1 year warranty standard. Extended warranty available.
- ROHS and Standard processing available
Maxwell-2 Block Diagram
Maxwell-2 Features
Size
WxLxH 71.65mm x 130mm x .062in nominal thickness not including connectors.
FPGA
Spartan 6 LX 45 with 43661 Logic Cells, 401 KBits distributed RAM, 58 DSP slices, 2088 Kb of block RAM, 2 memory controllers [1 in use for DDR], plus 8 DCM and 4 PLL to work with for custom frequencies. MicroBlaze ready.
DDR
128M x 16 DDR3 connected to FPGA memory management unit preferred pinout. Use to support MicroBlaze processor or for general purpose memory to support FPGA.
Clocks
100 MHz [differential input], 50 MHz, 25 MHz, 32.768 KHz, and 1 Hz inputs to FPGA.
FLASH
2 QSPI devices. One to configure FPGA and one for user purposes [1Gx8].
FRAM
8Kx8 memory for storing variables, configuations, real time status, recovering index etc.
RTC
Real Time Clock with coin cell [optional] back-up.
Ethernet
10/100 supported with RJ45
USB
Supported with mini USB connector
Bi-directional Parallel port
20 bits with direct connect to FPGA. 40 position locking header with alternate grounds
Output Parallel port
20 bits with buffered connection to FPGA. 40 position socket with alternate grounds. 3.3V 24 mA
Input Parallel port
20 bits with hysteresis receivers connection to FPGA. 40 position socket with alternate grounds
8 position switch
Dipswitch with user defined purpose. Suggest use for option selection - read with MicroBlaze and change program characteristics etc.
Push Button
Two push buttons provided for user defined purposes. Suggest for additional program input.
Power
Locking 2 x 3 header for 5V and Ground input. .6A typical. All internal references derived from this input.
Power Switch
2 position slide switch to disable/enable local power supplies.
LED
13 User LEDs plus additional status LEDs [100 MHz locked, Power Status]
Temperature
Read the current temperature of Maxwell. Device is located near FPGA and power supplies.
Maxwell-2 Benefits
Compact
Small package is easy to mount to almost any situation. Only 2.8"x5.12"x.062" in volume not including connectors.
Complete
Only 1 power reference required with Maxwell converting the 5V input power to DDR voltages plus 3.3, 2.5, 1.2 to support the FPGA and IO devices. With the MicroBlaze CPU and memory elements Linux can be implemented to operate your system. With the DDR and expansion FLASH reasonably large programs for an embedded system can be implemented. With the Ethernet and USB ports Maxwell can be used as a local controller or attach to other devices. Multiple parallel ports can be used for control. Additional Real Time Clock and Temperature inputs provide time tagging and system status. FRAM allows for parameter retention without programming the FLASH.
Ease of Use
Program in Vivado when using the MicroBlaze or ISE for non CPU designs. Direct download into the FPGA for immediate integration and easy programming of the QSPI for retained initialization at power up. The header [next to dipswitch] can be used as testpoints to see operation of selected signals within FPGA. LEDs can be used for status or other user purposes.
Availability
Standard Finish is stocked. ROHS built to order.
Part Number: Maxwell-2
Ordering Options
- Maxwell-2 Standard Maxwell-2 device. Add: -ROHS for ROHS compliant assembly
Maxwell-2 Drivers
Software SupportMaxwell-2 can be used with a pure VHDL design or using the embedded MicroBlaze CPU built into the FPGA. When using the MicroBlaze processor SW is used to operate. The initial boot code is stored within the QSPI with additional memory [local secondary QSPI] or USB/Ethernet attached devices as needed. The local DDR is available for expanded memory for execution. The FRAM can be used for parameter storage, snap-shots etc.
Integration support is available. Please contact Dynamic Engineering for this option or download the Technical Support Description from the Company button.
Integration support is available. Please contact Dynamic Engineering for this option or download the Technical Support Description from the Company button.