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PCI3IP
PCI adapter for 3 IP Modules. 8, 16, 32 bit accesses supported
PCI3IP Description
- Windows® , Linux driver included with purchase, VxWorks available.
- 32 bit PCI operation ↣ can be installed in any PCI position.
- 3 IndustryPack Module positions w/ 8⇆32 MHz. operation
- Fused, FIltered 5V, +12V, -12V supplied to IP´s
- Multi-word accesses supported including 32, 16, 8 bit
- Full memory space supplied to each position
- 1/2 length PCI card
- Ribbon Cable Bezel Cutout
- New Feature - VPWR - programmable 3.3V or 5V IP interface
- 1 year warranty standard. Extended warranty available.
- Extended [Industrial] Temperature standard.
- ROHS and Standard processing available
IndustryPack® Modules are an important part of solutions for Embedded situations. Rugged, small, light ... just right for many applications. IndustryPack® Modules require a carrier to adapt them to the system. Dynamic Engineering has carrier solutions for a variety of formats. PCI3IP is designed to support PC computer based solutions. Solutions available for PCIe, PC104p, cPCI, and VPX, with plans for for cPCIexpress, PC104express.
If you want to use IndustryPack® modules with your PCI system then PCI3IP is the choice for you. PCI3IP combines features you need with simplicity and speed. Up to 3 IP modules can be installed. Each position has independent operation - control, clocking, IO, power filtering and protection. PCI3IP is highly integrated with the PCI and IP interfaces closely coupled within the same FPGA. As a result the PCI3IP is faster, has a higher MTBF, and is easier to use than competing designs. There are fewer initialization steps and fewer PCI addresses to deal with and yet there are more features to work with. With the Windows 10 or Linux drivers operation can be "plug and play". PCI3IP is a mature design recently updated to revision 10 on the PCB. Thousands shipped and still in operation. Dynamic Engineering launched PCI3IP in 1999 and still supports today. Industrial Temperature components standard. Our base drivers are written to support both PCIe and PCI based IP carrriers allowing our IP drivers to be common for both bus types. This means an IP driver developed for PCI3IP will work with PCI5IP, PCIe3IP, PCIe5IP, cPCI2IP, cPCI4IP, VPX2IP, PCI104-IP etc. For newer platforms requiring PCIe please consider PCIe3IP and PCIe5IP designs.
PCI3IP is part of the IP Compatible family of modular I/O components. PCI3IP provides three IndustryPack® module sites in one PCI position. PCI3IP acts as an adapter, converter, carrier, and bridge between the PCI bus and your IndustryPack® hardware. PCI3IP is a half size, 32/33 PCI card compatible with the smallest chassis and all PCI slots.
PCI3IP is supported with Windows® compliant WDF drivers for Win10 etc. as well as Linux. The drivers come with a generic IP driver to allow use with "unknown" IP´s <=> IP´s that do not have a driver designed yet. For example, third party IP´s.
IndustryPacks are 16 bit devices, and the PCI bus supports 32 bit accesses. PCI3IP accepts up to 32 bits, and converts as required. Most modern CPU´s can generate 8, 16, and 32 and 64 bit transfers. The IP accesses can be auto-incremented or static address accesses. With the static access option the intended word can be accessed multiple times. With auto-incremented addresses multiple addresses are accessed. PCI3IP provides the capability of handling l32 bit words to reduce the average execution time. By changing from 16 bit accesses to 32 the overhead is cut in half leading to much higher bandwidth.
The Dynamic Engineering implementation does not require any special features on your IP module. Larger transfer sizes are especially useful for repetitive data transfers - loading or reading from RAM or FIFO´s faster will reduce the overhead on your CPU leading to more available time to process the data leading to lower cost or more capable systems.
Each position has a separate clock controller for 8 and 32 MHz operation. The frequency to be changed on the fly. The state-machine within the bridge design automatically locks to the IP Slot frequency as programmed.
PCI3IP is to tracks all accesses from the PCI bus. IP Modules can take longer than the PCI response specification leading to the use of retry cycles on the PCI bus. In a single CPU system the retry accesses are done serially. The current IP access will be the correct one to respond to the retry access. In a multi-CPU system it is possible to get out of sequence accesses, and potentially have the IP response sent to the wrong retry access. By storing the PCI parameters for the IP access and only responding to the correct retry cycle; multiprocessor cross contamination is avoided.
Each IP position has "self healing" fused, filtered power. Each IP Module has separate bulk and bypass capacitance.
Industry standard 50 pin [ribbon cable] headers are used with the IO connectors. Vertical connectors are provided in the rear two positions. The connector at the bezel is a right angle model and is mounted through the bezel. The bezel connector is outfit with ejectors. An ordering option for ejectors to be mounted to the rear vertical headers is available. This is not the default option due to PCI height restrictions. A recommended upgrade if your system has the room. "-EJ"
The bezel has a cut-out to allow the ribbon cables to be brought outside of the chassis without requiring an extra slot in the chassis. The blank bezel is available by adding "-BB" to the part number.
Ribbon cable or discrete wire cables can be interfaced directly with the PCI3IP. Alternatively the HDRterm50 can be used to create a terminal block interface.
The IP´s can be reset from the control register within the FPGA via the software interface. In addition at power-up the IP´s are provided the 200 mS reset as required by specification.
LED´s are provided to each of the three IP slots for activity indicators. When each slot is accessed the LED is flashed. The FPGA provides a "one shot" circuit to stretch the "on" time to make it visible. Power indicator LED´s are provided using voltage monitors. An additional eight user LED´s are available for debugging or other purposes.
A surface mount "dip switch" is available for configuration control or debugging purposes. The switch values are available to be read via the PCI bus. The switch is used for deterministic control by the driver. When multiple carriers are used in the same system the switch is used to allow the driver and application software to "know" which carrier maps to which handle. Further the slot information for a particular IP is stored to create a "vector" pointing to a specific slot on a specific carrier. Deterministic control of specific interfaces is easily achieved with this system without hardwiring system data into your software. The application software will be more portable and not break when new assets are added to the system (and your PCI addresses change).
IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the PCI3IP is created. The PCI3IP responds normally to the host, not creating an errror on the PCI bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have consequences.
Connector positioning is compatible with IP-Debug-Bus will allow the user to isolate and debug the control interface of an IP. The IP-Debug-IO can be used in conjunction with the PCI3IP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.
PCI3IP has an alternate "mini-map" option available. The standard design provides the full address space to the IP Memory space. The mini-map provides a minimized memory space equal to the ID, IO, and INT spaces with 128 bytes. The total PCI memory space is reduced to 2K with this option. Please download the alternate manual to get the address map and other details. Please order with the -MM option for the mini-map.
PCI3IP is an extended temperature board. This extended or "Industrial Temp" design has components rated for -40C to +85C minimum. This temperature range will need to be derated based on your chassis thermal situation.
With revision 11 and later PCI3IP has been upgraded to incorporate a Spartan 6. 3 new registers are added along with a new feature called "VPWR". VPWR is the voltage on the "5V" connection to the IP modules and terminations. The default is 5V to match the IP standard. The pin allocated to " Reserved 1" is monitored on each IP position and if any are grounded the voltage changes from 5V [open] to 3.3V [grounded]. The VPWR 5V LED is illuminated in open mode and VPWR 3.3V LED is illuminated for the RES1 = GND mode. This feature is being added to all Dynamic Engineering carriers as the transition to Spartan 6 is implemented. Please note: Previous revisions VPWR = 5V independent of RES1.
The benefit of VPWR: Most current FPGAs operate with 3.3V and are not 5V tolerant. To operate on the IP bus level shifters are required on both ends. IP Modules targeting Dynamic Engineering carriers for installation can remove the level shifters and ground the RES1 pin. In addition most IO does not require 5V and can use 3.3V to eliminate a power supply on the IP Module.
If you want to use IndustryPack® modules with your PCI system then PCI3IP is the choice for you. PCI3IP combines features you need with simplicity and speed. Up to 3 IP modules can be installed. Each position has independent operation - control, clocking, IO, power filtering and protection. PCI3IP is highly integrated with the PCI and IP interfaces closely coupled within the same FPGA. As a result the PCI3IP is faster, has a higher MTBF, and is easier to use than competing designs. There are fewer initialization steps and fewer PCI addresses to deal with and yet there are more features to work with. With the Windows 10 or Linux drivers operation can be "plug and play". PCI3IP is a mature design recently updated to revision 10 on the PCB. Thousands shipped and still in operation. Dynamic Engineering launched PCI3IP in 1999 and still supports today. Industrial Temperature components standard. Our base drivers are written to support both PCIe and PCI based IP carrriers allowing our IP drivers to be common for both bus types. This means an IP driver developed for PCI3IP will work with PCI5IP, PCIe3IP, PCIe5IP, cPCI2IP, cPCI4IP, VPX2IP, PCI104-IP etc. For newer platforms requiring PCIe please consider PCIe3IP and PCIe5IP designs.
PCI3IP is part of the IP Compatible family of modular I/O components. PCI3IP provides three IndustryPack® module sites in one PCI position. PCI3IP acts as an adapter, converter, carrier, and bridge between the PCI bus and your IndustryPack® hardware. PCI3IP is a half size, 32/33 PCI card compatible with the smallest chassis and all PCI slots.
PCI3IP is supported with Windows® compliant WDF drivers for Win10 etc. as well as Linux. The drivers come with a generic IP driver to allow use with "unknown" IP´s <=> IP´s that do not have a driver designed yet. For example, third party IP´s.
IndustryPacks are 16 bit devices, and the PCI bus supports 32 bit accesses. PCI3IP accepts up to 32 bits, and converts as required. Most modern CPU´s can generate 8, 16, and 32 and 64 bit transfers. The IP accesses can be auto-incremented or static address accesses. With the static access option the intended word can be accessed multiple times. With auto-incremented addresses multiple addresses are accessed. PCI3IP provides the capability of handling l32 bit words to reduce the average execution time. By changing from 16 bit accesses to 32 the overhead is cut in half leading to much higher bandwidth.
The Dynamic Engineering implementation does not require any special features on your IP module. Larger transfer sizes are especially useful for repetitive data transfers - loading or reading from RAM or FIFO´s faster will reduce the overhead on your CPU leading to more available time to process the data leading to lower cost or more capable systems.
Each position has a separate clock controller for 8 and 32 MHz operation. The frequency to be changed on the fly. The state-machine within the bridge design automatically locks to the IP Slot frequency as programmed.
PCI3IP is to tracks all accesses from the PCI bus. IP Modules can take longer than the PCI response specification leading to the use of retry cycles on the PCI bus. In a single CPU system the retry accesses are done serially. The current IP access will be the correct one to respond to the retry access. In a multi-CPU system it is possible to get out of sequence accesses, and potentially have the IP response sent to the wrong retry access. By storing the PCI parameters for the IP access and only responding to the correct retry cycle; multiprocessor cross contamination is avoided.
Each IP position has "self healing" fused, filtered power. Each IP Module has separate bulk and bypass capacitance.
Industry standard 50 pin [ribbon cable] headers are used with the IO connectors. Vertical connectors are provided in the rear two positions. The connector at the bezel is a right angle model and is mounted through the bezel. The bezel connector is outfit with ejectors. An ordering option for ejectors to be mounted to the rear vertical headers is available. This is not the default option due to PCI height restrictions. A recommended upgrade if your system has the room. "-EJ"
The bezel has a cut-out to allow the ribbon cables to be brought outside of the chassis without requiring an extra slot in the chassis. The blank bezel is available by adding "-BB" to the part number.
Ribbon cable or discrete wire cables can be interfaced directly with the PCI3IP. Alternatively the HDRterm50 can be used to create a terminal block interface.
The IP´s can be reset from the control register within the FPGA via the software interface. In addition at power-up the IP´s are provided the 200 mS reset as required by specification.
LED´s are provided to each of the three IP slots for activity indicators. When each slot is accessed the LED is flashed. The FPGA provides a "one shot" circuit to stretch the "on" time to make it visible. Power indicator LED´s are provided using voltage monitors. An additional eight user LED´s are available for debugging or other purposes.
A surface mount "dip switch" is available for configuration control or debugging purposes. The switch values are available to be read via the PCI bus. The switch is used for deterministic control by the driver. When multiple carriers are used in the same system the switch is used to allow the driver and application software to "know" which carrier maps to which handle. Further the slot information for a particular IP is stored to create a "vector" pointing to a specific slot on a specific carrier. Deterministic control of specific interfaces is easily achieved with this system without hardwiring system data into your software. The application software will be more portable and not break when new assets are added to the system (and your PCI addresses change).
IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the PCI3IP is created. The PCI3IP responds normally to the host, not creating an errror on the PCI bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have consequences.
Connector positioning is compatible with IP-Debug-Bus will allow the user to isolate and debug the control interface of an IP. The IP-Debug-IO can be used in conjunction with the PCI3IP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.
PCI3IP has an alternate "mini-map" option available. The standard design provides the full address space to the IP Memory space. The mini-map provides a minimized memory space equal to the ID, IO, and INT spaces with 128 bytes. The total PCI memory space is reduced to 2K with this option. Please download the alternate manual to get the address map and other details. Please order with the -MM option for the mini-map.
PCI3IP is an extended temperature board. This extended or "Industrial Temp" design has components rated for -40C to +85C minimum. This temperature range will need to be derated based on your chassis thermal situation.
With revision 11 and later PCI3IP has been upgraded to incorporate a Spartan 6. 3 new registers are added along with a new feature called "VPWR". VPWR is the voltage on the "5V" connection to the IP modules and terminations. The default is 5V to match the IP standard. The pin allocated to " Reserved 1" is monitored on each IP position and if any are grounded the voltage changes from 5V [open] to 3.3V [grounded]. The VPWR 5V LED is illuminated in open mode and VPWR 3.3V LED is illuminated for the RES1 = GND mode. This feature is being added to all Dynamic Engineering carriers as the transition to Spartan 6 is implemented. Please note: Previous revisions VPWR = 5V independent of RES1.
The benefit of VPWR: Most current FPGAs operate with 3.3V and are not 5V tolerant. To operate on the IP bus level shifters are required on both ends. IP Modules targeting Dynamic Engineering carriers for installation can remove the level shifters and ground the RES1 pin. In addition most IO does not require 5V and can use 3.3V to eliminate a power supply on the IP Module.
PCI3IP Features
Size
Half size PCI card.
IP compatible slots
3 independent positions.
Clocks
Each position has independent selection of 8 and 32 MHz operation. Clock selection can be changed on-the-fly with glitch free operation.
Access Width
Each position can be accessed as byte, word, or x32. Multiple word accesses can be static or auto-incrementing to the IP slot.
Bus Error
The Watch-Dog timer protects against PCI bus hangs by responding when the IP is not installed or has a failure.
Cable interface
Industry standard 50 pin box header connectors. Right angle through the bezel and vertical mount for the remaining 2 positions. Special bezel with cable slot for IO egress through the bezel. Bezel has an "arm" :rotate out of the way when installing the cable(s) and then lock back into place to secure.
Software Interface
Control registers are read-writeable. IO, ID, MEM, INT spaces supported. Windows® , Linux Drivers available
Interrupts
Each IP has 2 potential interrupts. All are transferred to the PCI bus. Control registers are provided to enable which interrupts are sent to the host and Status registers are provided to determine the source of the interrupt.
Power Requirement
+5V, +12V, -12V current determined by IP´s installed. 3.3V used by FPGA. Full IP spec power available to each position.
DIP switch
An 8 position switch is available to allow for configuration control, or to facilitate debugging, and to provide a positive ID of each PCI3IP in your system
LED´s
+5V, +12V, -12V and activity LED´s. 8 user LED´s also available.
Reliability
estimated 1.3 million hours. Bellcore. GB 25c
Export Classification
EAR99, HTS:8537.10.9050
PCI3IP Benefits
Speed
With the direct PCI to IP Bridge design featured in PCI3IP the access to your hardware happens faster than in competing designs. The 32 bit access capabilities further extends the lead in speed. Compatible with mult-processor systems without sacrificing access times for single CPU systems. Multiple threads with accesses to different IPs are supported.
Price
System level cost is best when reasonably priced reliable hardware is used and NRE minimized. With PCI3IP, driver support for the carrier and IP level, reference software, history of reliable operation, and fantastic client support your cost per unit and overall costs are attractive. Please check the current per item pricing with the storefront lower on this page. Orders can be placed via the on-line ordering system or via phone / email PO order systems.
Ease of Use
PCI3IP is easy to use. A point and shoot user interface to the IP sites. Please download the manuals and see for yourself. Reference software is provided in source form to get you started. The generic IP interface allows the driver to be used with IP´s without a driver specific to that design.
Availability
We work to keep PCI3IP in stock. Dynamic Engineering has in house manufacturing capabilities for short lead times on larger orders.
IP Specification Compatibility
PCI3IP is IP compliant per the VITA 4 - 1995 specification. All Dynamic Engineering IP Modules are compatible with the PCI3IP. All other IP Modules which are compliant with the VITA specification can be expected to work. ID, IO, INT, and Memory spaces are supported in all 3 positions.
PCI Compatibility
PCI3IP is a PCI compliant device. PCI3IP can be expected to work in any PCI compliant backplane.
Part Number: PCI3IP
Ordering Options
- PCI3IP Standard board - with 3 IP positions, Industrial temperature components. Add any of the following build options after the PN as shown below:
- -EJ Add Ejector Style Header connectors for the 2 non-bezel positions.
- -ROHS Use ROHS processing. Standard processing is "leaded"
- -BB Option to have a blank bezel without a cut-out. The Ribbon Cable Bezel is standard and includes a cutout to facilitate cable egress from the IP Modules. Note: -BB also causes bezel position to have a vertical box header connector.
- -VC Option to have vertical box header in bezel position while retaining the standard Ribbon Cable Bezel.
- -CC Option to add Conformal Coating
PCI3IP Drivers
Software Support for PCI3IP includes: Windows® 7, VxWorks, and Linux compliant drivers
Please see the Driver manuals for the specifics of each type.
PCI3IP Windows® or Linux drivers for PCI3IP. The drivers are designed to be overlayed with individual IP Module(s) driver(s). IP drivers are auto installed for each instance detected. Please see the Driver manual for the specifics of writing your board interface. Please contact Dynamic Engineering if you would like us to produce one for your IP or a third party design. Our Windows drivers come with IP-Generic which is automatically installed when a specific driver is not found for a particular IP Module. IP-Generic can be used to control your IP including handling interrupts, and accesses to all 4 space types.
Linux
The PCI3IP Linux driver is a bus driver capable of supporting multiple (up to 64) Industry Pack buses/carrier cards. This driver interfaces with the ipack-core Open Source code to support Industry Pack devices. This Open Source code has been slightly modified, and is included with the tar-ball for this driver.
A generic IPACK driver (ipack_gen) and user library (libipack) has been developed by Dynamic Engineering. This driver and library may be sufficient for developing user space drivers for a device depending upon the complexity of that device. Other device specific user libraries and kernel drivers are available for Dynamic Engineering Industry Pack modules. The diagram below illustrates possible layering of Industry Pack components:
Integration support is available. Please contact Dynamic Engineering for this option or download the Technical Support Description from the Company button.
Please see the Driver manuals for the specifics of each type.
PCI3IP Windows® or Linux drivers for PCI3IP. The drivers are designed to be overlayed with individual IP Module(s) driver(s). IP drivers are auto installed for each instance detected. Please see the Driver manual for the specifics of writing your board interface. Please contact Dynamic Engineering if you would like us to produce one for your IP or a third party design. Our Windows drivers come with IP-Generic which is automatically installed when a specific driver is not found for a particular IP Module. IP-Generic can be used to control your IP including handling interrupts, and accesses to all 4 space types.
Linux
The PCI3IP Linux driver is a bus driver capable of supporting multiple (up to 64) Industry Pack buses/carrier cards. This driver interfaces with the ipack-core Open Source code to support Industry Pack devices. This Open Source code has been slightly modified, and is included with the tar-ball for this driver.
A generic IPACK driver (ipack_gen) and user library (libipack) has been developed by Dynamic Engineering. This driver and library may be sufficient for developing user space drivers for a device depending upon the complexity of that device. Other device specific user libraries and kernel drivers are available for Dynamic Engineering Industry Pack modules. The diagram below illustrates possible layering of Industry Pack components:
Integration support is available. Please contact Dynamic Engineering for this option or download the Technical Support Description from the Company button.
PCI3IP Manuals
Click on the link to Download selected manuals in PDF format.
Download the PCI3IP HW Manual in PDF format. Memory Map, Bit Map, Operation, Pinouts etc. Please contact Dynamic Engineering if you need a previous revision manual.
Download the PCI3IP mini-map Manual 5/22/02 in PDF format.
Download the IP Carrier Windows®10 manual. For PCIe and PCI based carriers
Download the Win10 Generic IP Driver Manual in PDF format.
Download the IP Carrier and Module Quick Start guide for Windows®7
Download the IP Carrier Linux Manual
Download the Linux IP Module Manual
Download the PCI3IP HW Manual in PDF format. Memory Map, Bit Map, Operation, Pinouts etc. Please contact Dynamic Engineering if you need a previous revision manual.
Download the PCI3IP mini-map Manual 5/22/02 in PDF format.
Download the IP Carrier Windows®10 manual. For PCIe and PCI based carriers
Download the Win10 Generic IP Driver Manual in PDF format.
Download the IP Carrier and Module Quick Start guide for Windows®7
Download the IP Carrier Linux Manual
Download the Linux IP Module Manual