PC104p4IP

IndustryPack® Modules are an important part of solutions for Embedded situations. Rugged, small, light .. just right for many applications. IndustryPack® Modules require a "carrier" in most cases to adapt them to the system. Dynamic Engineering has carrier solutions for a variety of formats. PC104p4IP is designed to support PCI-104 solutions. Alternate types available available for VPX, cPCI, and PCI, PCIe and planned for cPCIexpress, PC104express.

PC104p4IP is part of the IP Compatible family of modular I/O components. PC104p4IP provides four IndustryPack® module sites in one PCI-104 stack position. PC104p4IP acts as an adapter, converter, carrier, and bridge between the PCI bus and your IndustryPack® hardware.

PC104p4IP is supported with Windows® compliant drivers as well as Linux support. The drivers come with a generic IP driver to allow use with "unknown" IPs ↔ IPs that do not have a driver designed yet. For example, third party IP modules.

IndustryPacks are 16 bit devices, and the PCI bus supports larger payloads. PC104p4IP converts to word accesses. Most modern CPU´s can generate 8, 16, 32 and 64 bit instructions. The IP accesses can be auto-incremented or static address accesses. With the static access option the intended word can be accessed multiple times. With auto-incremented addresses multiple addresses are accessed.

A typical system might have a PCI-104 CPU with Power supply in the PC104p stack and special purpose IO in the IP positions. PC104pPWR-28, PC104pCOOL [Fans], PC104pRPP [Reverse Power Protection and fan] are available options to support the PC104p side of the design. IP-1553, IP-429, IP-Parallel-IO, IP-BiSerial-VI and many more modules are available. A small, rugged system can be achieved in this manner. For more information on the above cards please use the menu system to navigate.

Multi-board operation is supported. With multiple PC104p4IP´s in your system and unique cabling, sensors etc. for each slot on each PC104p4IP it is important to "know" which PC104p4IP is which, and to properly control the IP modules mounted to them. A surface mount "dip switch" is provided to create an identifier for the software. A specific PC104p4IP can be matched with the PCI address allocated for deterministic control. The switch can also be used for other purposes; configuration control or debugging for example. The switch values are available to be read via the PCI bus.

The Dynamic Engineering implementation does not require any special features on your IP module. Larger transfer sizes are especially useful for repetitive data transfers - loading or reading from RAM or FIFOs faster will reduce the overhead on your CPU leading to more available time to process the data leading to lower cost or more capable systems.

Each position has a separate clock controller for 8 and 32 MHz operation. The frequency to be changed on the fly. The state-machine within the bridge design automatically locks to the IP Slot frequency as programmed.

Slots B/C and D/E are configured to accept two single IPs, or a double wide Industrypack compatible design. The data bus is designed to allow for 32 bit IP Bus operation. The data bus width is controlled by the address range the slot is controlled with. Automatic switching makes it possible to switch data bus size without changing the control registers for seamless operation.

Each IP position has "self healing" fused, filtered power. Each IP Module has separate bulk and bypass capacitance.

Industry standard 50 pin [ribbon cable] headers are used with the IO connectors. Vertical connectors are provided in all positions. Ribbon cable or discrete wire cables can be interfaced directly with the PC104p4IP. The traces between the IP IO connector and the PC104pIP IO connector have matched length [within .002"] for each slot independently. HDRterm50 can be used to create a terminal block interface.

The IP´s can be reset from the control register within the FPGA via the software interface. In addition at power-up the IP´s are provided the 200 mS reset as required by specification.

LED´s are provided to each of the IP slots for activity indicators. When each slot is accessed the LED is flashed. The FPGA provides a "one shot" circuit to stretch the "on" time to make it visible. Power indicator LED´s are provided using voltage monitors. An additional eight user LED´s are available for debugging or other purposes.

IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the PC104p4IP is created. PC104p4IP responds normally to the host, not creating an errror on the PCIe bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have consequences.

Connector positioning is compatible with IP-Debug-Bus will allow the user to isolate and debug the control interface of an IP. IP-Debug-IO can be used in conjunction with PC104p4IP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.