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ccPMC-SpaceWire
Use PMC adapter for PCIe applications
ccPMC-SpaceWire Description
- Windows®, Linux, or VxWorks driver available with purchase
- DMA on all channels
- 4 ports Rear IO with 1 transmitter and 1 receiver. BK models 200 MHz rated.
- Time Code support
- Two SW models: Standard and the new enhanced BK version
- 1 year warranty standard. Extended warranty available.
- Extended Temperature standard.
- ROHS and Standard processing available
Utilize SpaceWire to communicate with the European Space Agency and NASA equipment utilizing the ECSS-E-ST-50-12C specification. SpaceWire is configured using routers to create a heirarchical point-to-point system with high speed parallel paths. PMC-SpaceWire is frequently used as part of EGSE [Electronic Ground Support Equipment]. The conduction cooled version ccPMC-SpaceWire is usually preferred for launch equipment.
ccPMC SpaceWire implements SpaceWire in a convenient ccPMC format. With ccPMC you can install the adapter into PCI [PCIBPMCX1], cPCI [cPCI2PMC], PCIe [PCIeBPMCX1], or processor board PMC slots. The SpaceWire specification calls for LVDS signaling. The ccPMC version of the SpaceWire interface has the IO through the "user IO" connector "Pn4". The IO are chosen to match the differential routing used on many carriers. You can connect ccPMC-SpaceWire to other SpaceWire compliant devices without electrical interface issues.
Four fully independent and highly programmable LVDS IO channels are provided by the ccPMC-SpaceWire design. In the SpaceWire implementation the channels pass tokens between two independent state-machines to provide the proper protocol. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. ccPMC-SpaceWire provides a bridge from PCI <=> SpaceWire. Time code handing is supported for both generating and receiving / retransmitting. The local time can be transmitted at programmable intervals or time code received on the IO channels can be used internally as well as re-routed to the other channels.
Each channel has FIFO memory with [K/BK] 4/64 Kbytes TX and 4/64K bytes RX standard and up to 512K bytes as an option. The FIFO´s are 32 bits wide to optimize data transfer from the PCI bus. The base FIFO´s are internal to the FPGA and utilize dual ported RAM configured as a FIFO. Two external positions are available for larger FIFO´s to be installed to support one of the channels in both directions or two of the channels in one direction.
The bus interface is optimized to minimize the latency on the PCI bus. The loop-back test can be used for BIT, and for software development. The programmable FIFO flags are supported for interrupt or polled operation. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any debth to allow the software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size.
SpaceWire features automatic link testing when a node is brought on line - released for operation via software. The transmitter sends NULLs until NULLs are received and then sends FCT´s until FCT´ are received. The initial frequency is specified [ECSS-E-ST-50-12C] to be 10 MHz. Once the auto link test has passed, the hardware can switch to the programmed rate. A local oscillator is used to supply the 10 MHz reference clock for initialization. A programmable PLL is used to support operation once the link is established. The PLL is programmed via software and is referenced to the oscillator. Each channel has a separate PLL reference allowing the 4 channels to operate at different rates.
The SpaceWire protocol has flow control. The local memory on ccPMC-SpaceWire will not overrun. In situations where the data being sent to the ccPMC-SpaceWire card is not buffered it is recommended to use a "-128" model with large FIFO´s on channel 0. The issue is upstream - if there is an unbuffered or under-buffered data source that will loose data if the link is throttled back the larger FIFO´s will help. The larger FIFO´s will provide more room to accumulate data if the system is not ready to allow the ccPMC-SpaceWire to DMA transfer it immediately. The DMA transfers are higher bandwidth than the SpaceWire transfers allowing the system to catch-up once the DMA transfers restart. At 100 MHz and 80% data transfer the 128x32 FIFO will provide about 52 mS of data storage. The host would have to ignore ccPMC-SpaceWire interrupt requests for longer than 52 mS before throttling would occur. In most systems this is sufficient time to stay out of the throttled mode. To unload a full FIFO with DMA running it will take 128K/33M = .4mS => the unload to load multiplier is stongly in favor of the host side allowing the host to catch-up to the SpaceWire link once the delaying event has passed.
ccPMC-SpaceWire comes with Industrial temperature range parts installed.
ccPMC-SpaceWire is supported with the DESWBO Dynamic Engineering SpaceWire BreakOut tool for debugging SpaceWire systems, cables, carriers, and the DESWCB Dynamic Engineering SpaceWire Connector Board which provides a SpaceWire Cable to system cable interface.
If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!
ccPMC-SpaceWire Block Diagram
The standard timing uses the data and strobe to transmit and to receive the data. The data is transmitted as a command or data. The strobe provides the transitions for clocking when the data is unchanged between adjacent bit times.
ccPMC-SpaceWire Standard Timing
ccPMC SpaceWire implements SpaceWire in a convenient ccPMC format. With ccPMC you can install the adapter into PCI [PCIBPMCX1], cPCI [cPCI2PMC], PCIe [PCIeBPMCX1], or processor board PMC slots. The SpaceWire specification calls for LVDS signaling. The ccPMC version of the SpaceWire interface has the IO through the "user IO" connector "Pn4". The IO are chosen to match the differential routing used on many carriers. You can connect ccPMC-SpaceWire to other SpaceWire compliant devices without electrical interface issues.
Four fully independent and highly programmable LVDS IO channels are provided by the ccPMC-SpaceWire design. In the SpaceWire implementation the channels pass tokens between two independent state-machines to provide the proper protocol. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. ccPMC-SpaceWire provides a bridge from PCI <=> SpaceWire. Time code handing is supported for both generating and receiving / retransmitting. The local time can be transmitted at programmable intervals or time code received on the IO channels can be used internally as well as re-routed to the other channels.
Each channel has FIFO memory with [K/BK] 4/64 Kbytes TX and 4/64K bytes RX standard and up to 512K bytes as an option. The FIFO´s are 32 bits wide to optimize data transfer from the PCI bus. The base FIFO´s are internal to the FPGA and utilize dual ported RAM configured as a FIFO. Two external positions are available for larger FIFO´s to be installed to support one of the channels in both directions or two of the channels in one direction.
The bus interface is optimized to minimize the latency on the PCI bus. The loop-back test can be used for BIT, and for software development. The programmable FIFO flags are supported for interrupt or polled operation. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any debth to allow the software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size.
SpaceWire features automatic link testing when a node is brought on line - released for operation via software. The transmitter sends NULLs until NULLs are received and then sends FCT´s until FCT´ are received. The initial frequency is specified [ECSS-E-ST-50-12C] to be 10 MHz. Once the auto link test has passed, the hardware can switch to the programmed rate. A local oscillator is used to supply the 10 MHz reference clock for initialization. A programmable PLL is used to support operation once the link is established. The PLL is programmed via software and is referenced to the oscillator. Each channel has a separate PLL reference allowing the 4 channels to operate at different rates.
The SpaceWire protocol has flow control. The local memory on ccPMC-SpaceWire will not overrun. In situations where the data being sent to the ccPMC-SpaceWire card is not buffered it is recommended to use a "-128" model with large FIFO´s on channel 0. The issue is upstream - if there is an unbuffered or under-buffered data source that will loose data if the link is throttled back the larger FIFO´s will help. The larger FIFO´s will provide more room to accumulate data if the system is not ready to allow the ccPMC-SpaceWire to DMA transfer it immediately. The DMA transfers are higher bandwidth than the SpaceWire transfers allowing the system to catch-up once the DMA transfers restart. At 100 MHz and 80% data transfer the 128x32 FIFO will provide about 52 mS of data storage. The host would have to ignore ccPMC-SpaceWire interrupt requests for longer than 52 mS before throttling would occur. In most systems this is sufficient time to stay out of the throttled mode. To unload a full FIFO with DMA running it will take 128K/33M = .4mS => the unload to load multiplier is stongly in favor of the host side allowing the host to catch-up to the SpaceWire link once the delaying event has passed.
ccPMC-SpaceWire comes with Industrial temperature range parts installed.
ccPMC-SpaceWire is supported with the DESWBO Dynamic Engineering SpaceWire BreakOut tool for debugging SpaceWire systems, cables, carriers, and the DESWCB Dynamic Engineering SpaceWire Connector Board which provides a SpaceWire Cable to system cable interface.
If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!
The standard timing uses the data and strobe to transmit and to receive the data. The data is transmitted as a command or data. The strobe provides the transitions for clocking when the data is unchanged between adjacent bit times.
ccPMC-SpaceWire Features
Size
Standard Single ccPMC - 74mm x 143.75mm
Transmit Speeds
10 MHz initial rate per SpaceWire Specification. Software selectable secondary rate for transmit channel. Max. [K]frequency currently 180 Mhz. BK models rated at 200 MHz. Oscillator and programmable PLL combined for user frequency support.
PCI Speed
Standard 33 MHz. operation. DMA support or standard R/W operations, DMA is independent per channel - each channel has a separate controller to allow long data transfers with minimal CPU overhead and increased performance.
PCI Access Width
Standard 32 bit operation supported
Software Interface
ccPMC registers are read-writeable. Transmit and Receive functions separated.
Interrupts
Transmit and Receive state-machines, FIFO Programmable almost empty [transmit] and programmable almost full [receive] have programmable interrupts. Status can be polled for non-interrupt driven operation as well. Time Code interrupt.
Signaling
LVDS interface devices are utilized.
IO Interface
IO is available [4 ports] via Pn4. The differential IO is routed with controlled impedance, and matched lengths on each of the pairs.
Interface
ECSS-E-ST-50-12C specification compliant. Time Code supported.
Specification
ccPMC specification compliant
Power
5V and 3.3V from ccPMC connector with 2.5V, 1.2V, (1.8V) converted with on-board regulators.
Memory
Separate FIFO´s are provided for TX and RX of each channel. Internal Block RAM creating 4K[K model] 64K[BK model] is standard for all channels. 128K x 32 is available on port 0. Add -128 to part number for this option -128RX uses the external FIFO´s for port 0 and port 1 RX path.
Statement of Volatility
DIP switch
An 8 position switch is available to allow for configuration control, multiple ccPMC SpaceWire boards, and to facilitate integration
ccPMC-SpaceWire Benefits
Speed
ccPMC-SpaceWire is optimized for serial interfacing requirements. The FIFO memories and programmable interrupts off-load the CPU from most of the management other implementations require. FIFO access is optimized for the PCI bus further reducing overhead by speeding up the data transfer. On the IO side the PMC SpaceWire has independent and interconnected port functions. All ports can operate at maximum rate in parallel.
Price
ccPMC-SpaceWire is available off-the-shelf at a reasonable price. Custom versions can also be arranged. ccPMC SpaceWire is easily programmed to implement new functions. Previously implemented "custom designs" are available too. Without the costs of schematic level design, layout, debugging etc. A modified SpaceWire will represent a large cost and time savings in your budget.
Ease of Use
ccPMC-SpaceWire is easy to use. Point and shoot - just fill the FIFO and set the start bit to get your custom protocol transmitting. Built in loop-back capabilities and reference software help with integration into your system. Windows® Linux and VXWorks driver(s) available.
Availability
Dynamic Engineering works to keep ccPMC-SpaceWire [K and BK] in stock. Send in your order, and in most cases have your hardware fast. With custom designs a few week design period is usually required. We can support immediately with the std version, then send updated FLASH files later to help get your project going - right away.
Size
ccPMC-SpaceWire is a standard single width ccPMC card, and meets the ccPMC mechanical specifications. PccMC-SpaceWire can be used in all ccPMC positions [universal voltage]
ccPMC Compatibility
ccPMC-SpaceWire is ccPMC compliant per the IEEE 1386 specification.
PCI Compatibility
ccPMC-SpaceWire is PCI compliant. You can develop with a PCI e) to PMC adapter - PCI2PMC, PCIeBPMCX1 etc.
Part Number: ccPMC-SpaceWire
Ordering Options
- ccPMC-SpaceWire Standard board - Standard version with 4Kb FIFO per channel, standard SpaceWire [ECSS-E-ST-50-12C] timing and protocol. Independent DMA channels and Timecode support. Four ports through Pn4.
Order combinations of the options by simply adding the extension(s) to your order request.
-128 - Standard version with 4Kb FIFO per channel plus 512K [128K x 32] FIFO´s added to port 0 [TX and RX], standard SpaceWire [ECSS-E-ST-50-12C] timing and protocol. Independent DMA channels and Timecode support. Three channels through the Bezel and 1 on Pn4
-128RX - Standard version with 4Kb FIFO per channel plus 512K [128K x 32] FIFO´s added to channel 0 and 1 on RX, standard SpaceWire [ECSS-E-ST-50-12C] timing and protocol. Independent DMA channels and Timecode support. Three channels through the Bezel and 1 on Pn4
-BK - BK version with 64Kb FIFO per channel, standard SpaceWire [ECSS-E-ST-50-12C] timing and protocol. Independent DMA channels and Timecode support. Updated version recommended for new designs.
-CC - add Conformal Coating
-ROHS - add ROHS processing
ccPMC-SpaceWire Drivers
Software Support is supplied in the form of Win7, Linux, and VxWorks packages. The manuals are available on the SpaceWire Summary page.
ccPMC-SpaceWire Manuals
Hardware. The Hardware manuals for K amnd BK models plus related products are available on the SpaceWire Summary page.