PCI-ECL-II

Do you feel the need for speed? Differential ECL / NECL is still the interface of choice for high speed in noisy environments. PCI-ECL-II is an upgrade to the original PCI-ECL design. The IO connector pinout is maintained to allow ease of porting to the new platform. 20 ECL Inputs and 20 ECL Outputs plus 12 TTL IO are controlled via the FPGA. NECL, LVPECL and other ECL translators can be installed to meet IO requirements. The IO are matched length and impedance controlled. The Spartan VI FPGA provides the PCI interface, SDRAM interface, and IO interface with plenty of room for control, storage, filtering. and other control functions. With the SDRAM controller design, data can be stored for retransmission and looped if desired. The SDRAM can also be configured for FIFO like data handling. All options are selectable with software.

PCI-ECL-II features an integrated PCI interface with DMA support and ECL/TTL IO. The Spartan VI FPGA ties the PCI bus to the IO with storage and processing. Several models are offered and Dynamic Engineering can design a customized solution for you. See the partial list of available designs implemented on PCI-ECL and PCI-ECL-II. The Xilinx is reconfigurable, and supported with reprogrammable FLASH. Windows® and Linux SW solutions can be provided.

The ECL IO is routed to provide 100 ohm differential impedance, and matched length from the pin edge on the D100 connector to the Xilinx [BGA] Ball. All of the TX are matched, and all of the RX are matched to allow for high speed designs with tight timing requirements. Several ECL input bits are tied to clock capable input pins on the Xilinx to allow for external reference clocks.

The Xilinx is supported by a programmable PLL. The PLL is programmed with a serial bus via the Xilinx control register set. The driver handles this function. We recommend using the Cypress calculator to determine the PLL settings. The PLL supplies four clocks to the Xilinx which can be used for custom state-machine support.

In addition to the PLL, a client selected oscillator position is supplied. The default oscillator frequency is 50 MHz. and is used as the reference for the PLL. The oscillator frequency can be changed if required.

The ECL section has 20 inputs and 20 outputs. The state-machine can be programmed to use any number of the IO. The remaining IO can be used for a general purpose parallel port. Serial and Parallel interfaces can be implemented. For example, with a 4 wire serial interface a 16 bit parallel port will be available.

The SDRAM and internal Block RAM are used to store data from reception or for transmission. The memory is large enough that the IO can operate without interruption. The system can "go away" and not under or over-flow the memory. SDRAM is 32 MBytes in size per device. There are two devices on the board. Assuming a TX/RX channel on each SDRAM and allocating ½ of the memory to TX and to RX there are 16 MBytes per function. Further, assuming a continuous transmission is being supported, a 100 Mbit/sec serial data link, and DMA operation in use; the memory will support 1.34 seconds of system interruption. Similarly the Rx side can operate for 1.34 seconds before overflowing [assuming no handshaking in the design]. The memory can be allocated in software providing for asymmetrical operation, all on TX or all on RX for example.

The SDRAM can also be configured to retransmit data. The memory can be partitioned into a header, body, and tail. The body can be repeated a programmable number of times. The header => body=>tail loop can then be repeated or stop at completion. All under software control. In continuous mode interrupts can be generated at the end of each major loop. The boundaries are programmable to allow for customized sizes.


The Internal FIFO is to support DMA. The data is pipelined into or out of the FIFO under control of the scatter gather DMA engine. Data can also be moved with non DMA read or write operations. Data stored into the FIFO is moved to the main memory (SDRAM) and vice-versa. A state-machine moves the data with a burst transfer when there is sufficient data to move, and single transfers when near the boundary conditions. The state-machine for the data transfer operates autonomously. Each function has a separate DMA engine to allow for parallel TX and RX operation without software intervention.

Multi-board operation is supported. With multiple PCI-ECL-IIs in your system and unique cabling, sensors etc. for each slot it is important to "know" which PCI-ECL-II is which. A surface mount "dip switch" is provided to provide an identifier to the software. A specific PCI-ECL-II can be matched up with the PCI address allocated to make for deterministic control. The switch can also be used for other purposes; configuration control or debugging for example. The switch values are available to be read via the PCI bus.

The reprogrammable FLASH memory stores the Xilinx design file. The JTAG header is used to load the FLASH using the Xilinx standard IMPACT® software and download cable.

The IO is brought to a "D100" connector. The connector on PCI-ECL-II is a available in the standard right angle or a vertical mount. The right angle connector mounts through the bezel allowing for IO outside of the chassis. The vertical connector is used with a blank bezel and is optimized for internal to the chassis IO requirements. The mating connector is the AMP 5749621-9. Dynamic Engineering has cables and a break-out for this connector. HDEterm100 can be used to create a terminal block interface. HDEcabl100 is the standard cable. Customer specific cables can be manufactured. Please forward your connector and pin assignment requirements if you are interested in custom cables. In addition Dynamic Engineering has a "cross over" cable which can be used to interconnect two PCI-ECL-II cards or to connect to your equipment if you adopt the connector definitions that we used. The Pinouts are available within the manuals.


Block Diagram of PCI-ECL-II