cPCI-DartBase

cPCi-DartBase was designed in 2008. This webpage is provided for reference purposes. If you like the concept and want to purchase we can update the design to be manufacturable with current parts etc. We can also enhance the design to make use of the newer FPGAs. In addition, PCIe-AlteraCycloneIV is available with PCIe-Spartan-VI due for release. The Spartan VI derivative is planned to be ported to cPCI to provide a user programmable solution for this platform. Please contact Dynamic Engineering for more information on either of the Spartan Vi products.

Do you need to develop your own cPCI application HW and prefer a mezzanine approach? Dynamic Engineering offers a line of PMC carriers and the cPCI-DartBase for this purpose. The advantages of "DartBase" include access to more of the cPCI 3U bezel, more built in power options, more surface area for the mezzanine and fewer pins required for the bus interface. Analog, Digital and mixed designs are supported with the clean power supplies and tied at the connector analog and digital return paths. For PXI chassis the clocks and timing control signals are routed to the mezzanine position.

Power from the cPCI system is routed to the mezzanine connector to support the +/-12V, 3.3 and 5V rails. In addition the 5V is used with buck and boost supplies to create +/- 6V power rails. The 6V rails are provided to the mezzanine and used to generate the 1.25V and 2.5V ref voltages through linear supplies to serve as analog references. 1.5A of 2.5V analog power is also supplied with a linear regulator from the 3.3V supply for operating analog circuits. Approximately 2A each of 1.2V and 2.5V power is supplied to operate an FPGA´s core voltages. The analog and digital grounds are tied together via 6A ferrite bead. The analog voltages can be used for digital purposes if desired.

When installed in a PXI chassis the system clock and triggers may be available. PXI_TRIG0 - PXI_TRIG7, PXI_CLK10, and PXI_STAR are routed from J2 to the mezzanine control connector.

JTAG programming can be used to update FLASH on the mezzanine card. A header mounted to the DartBase is routed to the mezzanine connector. In addition the control and programming lines are tied between a port on the local FPGA and programming port on the mezzanine FPGA to allow reprogramming on-the-fly. The DartBase design has the logic and the Driver supports reprogramming the mezzanine FPGA for reprogrammability. A handy feature for development and field based updates. Please note: the target FPGA is a Spartan family part. DartBase may need to be updated to support an Altera based design in this manner.

In PCI based systems the address of the installed cards is unknown until run time. With multiple cards of the same type in a system SW designers run the risk of controlling the wrong assets or making decisions based on the wrong input. The DartBase design includes a simple remedy. An octal switch is provided for positive identification of an individual card in a multi-card environment. The driver for the card can read the switch and allow the application software to make a positive association between a specific card and its "handle".

Many times you need more than one port of the same type, or several different ports on the same card. There are 8 channels designed into the DartBase structure to allow for up to 8 devices [same or different] to be directly controlled and with individual DMA capability. The DartBase design includes the DMA arbitration and memory elements to support DMA access or standard R/W access on each channel. In addition there is a control link which can be used to do top level set-up and control. As an example you can put 8 ports on the mezzanine each with DMA transmit and DMA receive support. Each port can operate independently with the DartBase architecture. The first mezzanine developed has 8 channels of Analog circuitry to stimulate and read-back data for a biometrics application.

The DartBase design is intended to be flexible allowing for a variety of connectors at the bezel, types of IO implemented etc. The Bezel for DartBase is designed to accomodate wider connectors than on PMC and other standard mezzanine cards.

"Zero Slot fans"™ can be installed to provide direct cooling to the main component side of the installed mezzanine. The fans provide approximately 5 CFM each.

The single width PMC specification is for 149x74 mm [5.866" x 2.91"] with area lost for 4 PMC connectors and 2 voltage keying holes. The DartBase design uses LVDS ports to communicate between the mezzanine and the Base allowing 8 channels plus the control channel to reside in one connector. Power is through a second connector. Since LVDS levels are defined there is no need for voltage keying holes. The area of the Dart Mezzanine has been expanded to be 6.293" x 3.7". The added area coupled with the reduced connectors and holes provides for more usable space. In addition the connector mounting positions are set to allow the FPGA to be mounted below the connectors and the IO above. This configuration allows for better performance with mixed analog and digital circuitry.

To make integration easy an engineering kit is available. The engineering kit includes an Altium compatible project to help ensure your mezzanine fits properly. If you choose to use one of our standard mezzanines you can get the VHDL for it to allow you to make changes for your project. A windows® driver is also part of the engineering kit. Linux is available upon request. The driver makes accomodations for user defined registers - for when you do your own project and do not want to write your own driver.

Frequently clients ask Dynamic Engineering to do the initial programming for their project and then deliver a custom engineering kit with the initial implementation of the mezzanine, custom driver and manuals to them. In this state the client can do the maintenance or add features while taking advantage of Dynamic Engineering´s expertise and familiarity with cPCI-DartBase. Dartmouth worked with Dynamic Engineering to develop the "DartBoard" depicted in the combined block diagram.