ccPMC-Parallel-TTL

Does your system require single ended TTL or CMOS level signals? How about medium speed Analog data capture [ADC 1-10 MHz]? Dynamic Engineering has a multitude of solutions covering different architectures and mezzanine types. With most architectures you have a choice with carriers for cPCI, PCI, PCIe, VME, VPX, PCI-104, and other buses for XMC, PMC and IP mezzanine modules. Usually your choice is based on other system constraints as various modules can provide the IO you require. Dynamic Engineering can assist in your decision making regarding architecture and other trade-offs. Dynamic Engineering has carriers for most architectures, and is adding more as new solutions are requested by our clients.

The Conduction Cooled PMC compatible ccPMC-Parallel-TTL has build options to have up to 64 independent digital IO and up to 8 ADC channels. The high density makes efficient use of precious PMC slot resources. The IO is available for system connection through the rear [Pn4] connector. The rear panel IO has a PIM and PIM Carrier available for rear panel wiring options. The HDEterm68 can be used as a breakout for the rear panel IO when the PMC carrier has a SCSI style connector for the rear IO. The HDEcabl68 provides a convenient cable. The pin definitions are consistent with the PMC Parallel IO and PMC Parallel TTL designs to enable users to migrate to the ccPMC-Parallel-TTL quickly and easily when a conduction cooled solution is required.

Each TTL IO is independently programmable. The outputs can be enabled and driven high or low. When disabled on-board pull-ups terminate the lines. The pull-ups can be referenced to 5V or 3.3V as an ordering option. A master enable is available to allow the user to synchronize the upper and lower outputs for coherant 64 bit operation in a 32 bit system. The master enable can be set to allow independent upper and lower bank updates.

All TTL channels can be read as inputs regardless of the transmit enable programming. Local loop-back can be used for BIT. All IO channels can be used as interrupt generators. Interrupts are programmable to be based on either or both edges for "Change of State" operation. An external clock, PCI clock, or oscillator can be selected for the reference on the COS operation. The reference can be programmed to be divided to create lower frequencies. A PLL is available to support user frequency selection to provide the right sampling rate for your application.

All of the IO are routed through the FPGA device to allow for custom applications that require hardware intervention or specific timing. For example the design of the ccPMC Parallel TTL supports internal FIFOs and DMA. With an added state-machine for your interface the hardware can provide much more than a simple parallel interface. Contact Dynamic Engineering for convenient customer specific implementations.

ccPMC-Parallel-TTL has an option to remove some of the TTL and replace them with ADC. The lower 32 bits can be removed and 8 - 12 bit ADCs installed instead. Each ADC can be programmed to operate at frequencies up to 10 MHz. Options for synchronous sampling across channels and independent reference frequencies under software control. The ADCs can be programmed for different voltage ranges with a pair of resistors. The ADC is a 0-5V model. WIth matching resistors 0-10V is scaled etc. Each ADC has a high bandwidth opamp buffer to support high frequencies with low current requirements [in the input signal]. Please contact Dynamic Engineering with your requirements.

Each of the ADC channels can be supported with memory, DMA, data/signal processing, etc. For example; The BA18 version of ccPMC Parallel TTL has 32 TTL lines, and 8 ADCs. Each ADC has a separate DMA channel and FIFO memory support. The data is sampled and tested against the current reference sample. When the new sample exceeds the range established by the current sample it is saved into the FIFO along with the Time Tag and used as an updated reference sample. The range is programmable [ sample - lower offset <=> sample + upper offset]. With the Time Tag a known number of in range samples occurred between the data stored. Data reduction at the source reduces CPU processing later and bus overhead. Tell us what features you require.

The base model has a simple to use register based interface. The registers are mapped as 32 bit words. All registers are read-writeable. The Windows® compatible [XP/2000] driver is available to provide the system level interface for this design. Use standard C/C++ to control your hardware or use the Hardware manual to make your own software interface. The manuals for the different implementations are available for download from the bottom of this page.

All parts are industrial temp or better [-40C <=> +85C]. Conformal coating, thermal gluing and thermal foam are available options help adapt to your environment.